Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-02-09
2001-07-31
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S624000, C438S637000, C438S700000, C438S734000, C438S737000
Reexamination Certificate
active
06268283
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for fabricating multilevel interconnects, and more particularly, to a method for manufacturing a dual damascene structure.
2. Description of Related Art
As the initegration of a semiconductor device is increased, the resistance-capacitance dela resulting from the parasitic capacitance generated by an inter-metal dielectric layer is worsened. Hence, it is common to utilize a low-permittivity dielectric to form an inter-metal dielectric in a sub-micron semiconductor. In the damascene process, the low-permittivity dielectric layer is usually used to reduce interconnection parasitic capacitance, hence the operation speed is improved. Therefore, the low-permittivity dielectric layer is a very popular IMD material for use in high-speed integrated circuits (IC).
A dual damascene process is a technique which imbeds metal plugs into an insulator and forms an aluminum metal layer on the substrate to connect the metal plugs. The dual damascene process is a process for manufacturing metal lines with high reliability and low cost. Materials used in the interconnections are not limited by the etching process of the metal. As a result, the dual damascene structure has been widely used in the manufacturing process for copper conductive lines so that the resistance of the conductive line is reduced for increasing the operation speed and quality of the integrated circuit. As the integration of a semiconductor device is increased, the dual damascene structure using dielectric layers with low-permittivity is used more in the semiconductor processes for manufacturing metal interconnections.
FIGS. 1A through 1D
are schematic, cross-sectional views showing a conventional method for fabricating a dual damascene structure.
Referring to
FIG. 1A
, a substrate
100
contains a metal layer
102
is provided. A dielectric layer
104
, an etching stop layer
106
and a dielectric layer
108
are formed on a provided substrate
100
, in sequence. A photoresist layer
110
is then formed on the dielectric layer
108
. A conventional photolithography method is applied to pattern the photoresist layer
110
so as to form the pattern for a via opening.
Referring to
FIG. 1B
, the dielectric layer
108
etching stop layer
106
and dielectric layer
104
are etched to form the via opening
112
exposing the metal layer
102
, with the patterned photoresist layer
110
serving as a mask. The photoresist layer
110
is then removed followed by the step of forming another photoresist layer
114
on the substrate
100
. A conventional photolithography method is applied to pattern the photoresist layer
110
, so as to form a trench pattern.
Referring to FIG.
1
C. the dielectric layer
108
is then etched to form the trench
116
, with the photoresist layer
108
and etching stop layer
108
serving as a mask and etching stop point, respectively. Thereafter, the photoresist layer
114
is removed. The trench
116
and via opening
112
are then filled with a metal layer
118
so that a dual damascene structure is formed, as shown in FIG.
1
D.
As the integration of a semiconductor device is increased, the resistance-ecapacitance delay resulting from the parasitic capacitance generated by an inter-metal dielectric layer is worsened. Hence, it is common to utilize a low-permittivity dielectric to form an inter-metal dielectric in a sub-micron semiconductor fabrication process for reducing the Resistance-Capacitance Time Delay effect. Conventionally, the photoresist layer is composed of polymer materials and the low-permittivity dielectric also includes organic materials. However, the regions
120
of the dielectric layers
108
and
104
exposed in the via opening
112
may be damaged by the developer during the developing process of the photoresist layers
110
and
114
. Therefore, the profile of the dual damascene is destroyed.
SUMMARY OF THE INVENTION
The invention provides an improved method for forming a dual damascene structure. The method includes forming a first dielectric layer, an etching stop layer, a second dielectric layer and a hard mask layer on the substrate. Parts of the hard mask layer, the second dielectric layer, the etching stop layer and the first dielectric layer are etched to form a via opening. A non-conformal cap dielectric layer is then formed on the hard mask layer to cover the top region of the via opening. A patterned photoresist layer is then formed on the non-conformal cap layer. Parts of the non-conformal cap layer hard mask layer and second dielectric layer are etched to form a trench by using the patterned photo-resist layer as an etching mask. The patterned photoresist layer and non-conformal cap layer are then removed. The trench and via opening are then filled with a layer of conductive material. A chemical mechanical polishing step is then performed to remove redundant portions of the conductive layer.
The cap layer is for example, composed of a material capable of preventing the damage in the developing step of the photoresist layer. Moreover, the first and second dielectric layers are protected in the developing step of the photoresist because the cap layer only covers the top region of the via opening. Therefore, the original profile of the via opening is maintained. The cap layer can be formed by a plasma enhanced chemical vapor deposition process. The cap layer includes silicon oxide, silicon nitride or silicon oxynitride. Furthermore, the cap layer can be removed easily using a dry etching.
REFERENCES:
patent: 5920790 (1999-07-01), Wetzel et al.
patent: 6057239 (2000-05-01), Wang et al.
patent: 6100184 (2000-08-01), Zhao et al.
Ikeba et al, Integration of Organic Low-k Material with Cu-Damascene Employing Novel Process, Interconnect Technology Conference 1998, pp 131-133, Jun. 01, 1998.
Bowers Charles
Pham Thanhha
United Microelectronics Corp.
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