Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
1998-02-04
2001-04-17
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S622000, C438S623000, C438S624000, C438S637000, C438S778000, C438S781000, C438S791000, C438S395000, C427S096400, C427S189000, C427S204000, C427S214000, C148SDIG008
Reexamination Certificate
active
06218318
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices and more particularly to a high-speed semiconductor device with an interlayer insulation film having a low permittivity.
In a semiconductor integrated circuit in which a large number of semiconductor devices are integrated on a common substrate, a multilayer interconnection structure is generally used for interconnecting the semiconductor devices. In such a multilayer interconnection structure, a first-layer interconnection pattern is covered by a first-layer interlayer insulation film, and a second-layer interconnection pattern is provided on such a first-layer interlayer insulation film. The second-layer interconnection pattern is then covered by a second-layer interlayer insulation film and a third-layer interconnection pattern is provided on the second-layer interlayer insulation film.
When using such an interlayer insulation structure in high-speed semiconductor devices such as a logic device or a high-speed memory device, it is desired that the insulation film forming the interlayer insulation film has a permittivity as low as possible. In an extremely miniaturized semiconductor device called sub-halfmicron devices in which the design rule is 0.3 &mgr;m or less, in particular, there is a tendency that an electrostatic induction between adjacent conductor patterns invites an increase in the impedance, which in turn causes a delay in response or increase of the electric power consumption.
On the other hand, the insulation film used for such an interlayer insulation film is required to form a flat, planarized structure in view of the fact that a further conductor pattern may be formed thereon, so that the conductor pattern formed on the interlayer insulation film is not disconnected by a stepped structure formed on the interlayer insulation film. Such a planarization of the interlayer insulation film is also essential in view of the process of formation of the minute interconnection pattern, which is conducted by using a high-resolution optical exposure system. As the interlayer insulation film is provided so as to bury the underlying conductor patterns, it is necessary that the interlayer insulation film is applied in a low-viscosty fluid state such that the shape of the conductor pattern is not transferred to the surface of the interlayer insulation film.
In view of the foregoing, it has been practiced to form an interlayer insulation film having a planarized top surface by depositing an SiO
2
film by a high-density plasma CVD process, followed by a chemical mechanical polishing process (CMP). However, the insulation film formed according to such a process has a permittivity of about 3.5 or higher even in the case in which a F-doping is conducted to the SiO
2
film. Further reduction of the permittivity is extremely difficult.
It is also known that a low-permittivity interlayer insulation film may be obtained by using F-doped polyimide or a fluorocarbon resin in place of the conventional CVD-SiO
2
films. Such organic insulation films are formed typically by a coating process such as a spin-coating process. By using the organic insulation film, the permittivity of the interlayer insulation film can be reduced to about 2.
On the other hand, such organic insulation film suffers from a problem of poor adhesion and there is a tendency that the insulation film peels off. Further, the organic insulation film has a problem in that the adhesion to a resist film, which is used for patterning the conductor patterns, is also unsatisfactory. In addition, the organic insulation film has a problem of poor resistance to various chemicals used in the fabrication process of semiconductor devices or to a plasma process conducted in an oxygen plasma.
Further, it is proposed to use a film-forming organic silica known as SOG for the interlayer insulation film. An SOG is a liquid formed of a partial hydrolysis of alkoxysilane. In this case, too, a silica film having a permittivity of about 2.5 is obtained. However, such an SOG film also suffers from the problem of poor adhesion to the underlying layer. In a typical case of the conventional SOG film that is formed of a hydrolysate of alkoxysilane or halonagated silane, the density of the Si—O—Si bonds in the film is reduced due to the existence of a hydrogen atom, fluorine atom or organic group bonded to the Si atoms, and there appears various problems, although the film may have a low permittivity as noted before, such as poor thermal stability caused as a result of poor thermal stability of the functional groups forming the film, in addition to the problem of the poor adherence to the underlying layer.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and a fabrication process thereof wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a semiconductor device having an interlayer insulation film wherein the interlayer insulation film forms a spontaneous planarized surface even when provided on an irregular underlying structure.
Another object of the present invention is to provide a semiconductor device having an interlayer insulation film wherein the interlayer insulation film has low permittivity, excellent adherence to an underlying layer, high mechanical strength, high resistance to chemicals such as alkalis and high resistance to cracking.
Another object of the present invention is to provide a semiconductor device, comprising:
a substrate;
an interconnection layer provided on said substrate, said interconnection layer including an interconnection pattern; and
a porous interlayer insulation film provided on said interconnection layer so as to cover said interconnection pattern, said porous interlayer insulation film including a stacking of particles,
wherein said particles are formed of SiO
2
particles having a diameter in the range between about 5 nm and about 50 nm and stacked so as to form a void between adjacent particles, and
wherein said interlayer insulation film has a porosity in the range between about 13% and about 42%.
Another object of the present invention is to provide a semiconductor device, comprising:
a substrate;
a porous interlayer insulation film provided on said substrate, said porous interlayer insulation film including a stacking of particles; and
a CVD oxide film provided on said porous interlayer insulation film such that said CVD oxide film does not fill a void in said porous interlayer insulation film substantially,
wherein said particles are formed of SiO
2
particles having a diameter in the range between about 5 nm and about 50 nm, and
wherein said void is formed in said porous interlayer insulation film between said particles.
According to the present invention, the permittivity of the interlayer insulation film can be reduced substantially by forming the interlayer insulation film in a porous state, while maintaining excellent planarization.
Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising the steps of:
applying a film-forming liquid on an underlying structure, said film-forming liquid including therein SiO
2
particles and a binder; and
heating said underlying structure applied with said film-forming liquid to form an insulation film thereon such that said insulation film includes said SiO
2
particles and pores formed between said SiO
2
particles,
wherein said SiO
2
particles have a diameter in the range between about 5 nm and about 50 nm, and
wherein said step of heating is conducted at a temperature in the range between about 350° C. and about 400° C., in an inert gas atmosphere containing oxygen with a concentration of 1% or less.
According to the present invention, a porous interlayer insulation film having a low permittivity is formed with an excellent adherence to an underlying structure, while maintaining an excellent planarization.
Another object of the present invention is to provide a
Harada Hideki
Ohkura Yoshiyuki
Armstrong, Westerman Hattori, McLeland & Naughton
Bowers Charles
Fujitsu Limited
Kilday Lisa
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