Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
1998-09-22
2001-03-20
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S095000, C326S083000, C327S206000
Reexamination Certificate
active
06204696
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to circuits and, more particularly, to domino circuits.
2. Background Art
Wide-fanin gates are gates having numerous input ports. Wide-fanin gates are routinely employed on critical delay paths of high-performance datapaths, such as in a microprocessor, digital signal processor, or other semiconductor device. Dynamic/Domino logic techniques have been used to achieve substantially higher performance than are provided by static complementary metal oxide semiconductor (CMOS) technology for wide-fanin gates. For example, referring to
FIG. 1
, a conventional prior art domino OR gate
10
includes multiple inputs signals A
1
. . . An to n-channel field effect transistors (nFET devices) M
1
-
1
. . . M
1
-n, where n may 2 or more. In a wide-fanin gate, n is considerably greater than 2. Gate
10
also includes a precharge p-channel field effect transistor (pFET device) M
2
, a keeper pFET device M
3
, and a static CMOS output stage
14
, which is an inverter. During a precharge phase, input signals A
1
. . . An are predischarged to Vgnd and a clock signal (Clk) goes low. When Clk goes low, pFET device M
2
is turned ON and a domino stage output signal Q is pulled high to Vdd. As signal Q goes high, an inverter
18
turns on pFET device M
3
which keeps signal Q high after Clk transitions high, which turns off pFET device M
2
. During an evaluation phase, if one or more of input signals A
1
. . . An goes high, the corresponding nFET device(s) M
1
-
1
. . . M
1
-n is turned ON pulling signal Q low (Vgnd). When signal Q goes low, an evaluated output signal out at the output of output stage
14
goes high.
Performance is measured by how quickly signal Q goes low and the evaluated output signal goes high. However, the noise immunity of these techniques degrades with process scaling due at least in part to increasing domino-stage transistor leakage current. Recently, strategies to restore back the noise immunity have been proposed: these strategies involve modifying the gate structure by either employing multiple threshold voltages or noise-tolerant pMOS pull-up stages. However, these modifications reduce the performance advantage enjoyed by domino logic techniques over conventional static CMOS techniques.
Accordingly, there is a need for domino circuits with high performance and high noise immunity.
SUMMARY
In some embodiments, the invention includes a domino circuit having a precharge circuit including a source follower nFET device coupled to a domino stage conductor. An evaluation path circuit is also coupled to the domino stage conductor. A hysteretic output stage receives a signal from the domino stage conductor and provide therefrom an evaluated output signal.
In other embodiments, the invention includes a domino circuit having a predischarge circuit coupled to a domino stage conductor. An evaluation path circuit includes source follower NFET devices coupled to the domino stage conductor. A hysteretic output stage receives a signal from the domino stage conductor and provides therefrom an evaluated output signal.
In still other embodiments, the invention includes a domino circuit having a precharge circuit including coupled to a domino stage conductor. An evaluation path circuit is coupled to the domino stage conductor. An output stage includes an inverter to receive a signal from the domino stage conductor and to provide an evaluated output signal on an output conductor, the output stage including a duplicate evaluation path circuit coupled to an output conductor.
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Krishnamurthy Ram K.
Soumyanath Krishnamurthy
Aldous Alan K.
Chang Daniel D.
Intel Corporation
Tokar Michael
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