Method of adjusting the threshold voltage in an SOI CMOS

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

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C438S163000

Reexamination Certificate

active

06197624

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device manufactured by using a semiconductor thin film and a manufacturing method thereof. More specifically, the invention relates to a thin-film transistor (TFT) having a bottom-gate structure as typified by an inverted staggered structure.
In this specification, the term “semiconductor device” includes all devices capable of operation by utilizing semiconductor characteristics. That is, all of TFTs, electro-optical devices, semiconductor circuits, electronic apparatuses, and the like that are described in this specification fall under the category of the semiconductor device.
2. Description of the Related Art
The demand for active matrix liquid crystal display devices has increased rapidly in recent years, and it is now urgently needed to develop techniques for forming thin-film transistors (hereinafter abbreviated as TFTs) by using a semiconductor thin film formed on a glass or quartz substrate. The TFTs are used as switching elements for image display.
TFTs, which are formed on the same substrate as a group of as many as one million several hundred thousand pieces, should have given electrical characteristics depending on the function of an electrical circuit to form. Among those electrical characteristics of a TFT is a parameter called the threshold voltage (Vth).
The threshold voltage is defined as a voltage at which an inversion layer is formed in the channel portion of a TFT. That is, the threshold voltage is a voltage at which a TFT is switched from an off state to an on state. Therefore, it can be said that a TFT having a higher threshold voltage has a higher operating voltage.
There is a problem that the threshold voltage is varied by various extraneous factors such as contamination impurities in the active layer, fixed and mobile charges in the gate insulating film, interface states at the interface between the active layer and the gate insulating film, and a work function difference between the gate electrode and the active layer. Although the introduction of contamination impurities into the active layer and mobile charges into the gate insulating film can be prevented by cleaning a processing environment, fixed charges, interface states, and a work function difference are determined by the materials of the device and hence cannot be changed easily.
The above-mentioned extraneous factors may shift the threshold voltage to the plus or minus side. For example, if the threshold voltage of an NTFT becomes unusually low, there may occur a problem that current flows even in a state that the TFT should be kept off (i.e., in a state that no gate voltage is applied). This is called a normally-on state.
Especially, with respect to a TFT in which a laser crystallized amorphous semiconductor thin film is used for an active layer (so called low-temperature polysilicon TFT), threshold voltages of the NTFT and the PTFT are unusually high (4 to 6 V for the NTFT, −5 to −7 V for the PTFT), which is a serious problem.
A technique called the channel doping is known as a means for solving the above problem. The channel doping is a technique of obtaining a desired threshold voltage by forcibly shifting the threshold voltage by doping the active layer with an impurity at a proper concentration.
Examples of impurities used for the channel doping include Group 13 elements of B (boron), Ga (gallium), and In (indium) and group-15 elements of P (phosphorus), As (arsenic), and Sb (antimony).
SUMMARY OF THE INVENTION
An object of the present invention is to provide a technique for performing channel doping on a bottom-gate TFT (typified by an inverted staggered structure TFT).
Another object of the invention is to provide a semiconductor device including a plurality of bottom-gate TFTs of the invention and a manufacturing method thereof.
The invention provides a semiconductor device including a plurality of bottom-gate TFTs formed on a substrate having an insulating surface, wherein an impurity element for a threshold voltage control has been intentionally added to a channel forming region of at least an n-channel TFT or TFTs among the plurality of bottom-gate TFTs, and wherein the concentration of the impurity element in the channel forming region decreases as the position approaches an interface where the channel forming region and a gate insulating film are in contact with each other.
According to another aspect of the invention, there is provided a semiconductor device including a plurality of bottom-gate TFTs formed on a substrate having an insulating surface, wherein an element selected form Group 15 elements has been intentionally added to a channel forming region of an NTFT and an element selected form Group 13 elements has been intentionally added to a channel forming region of a PTFT among the plurality of bottom-gate TFTs, and wherein the concentrations of the elements in the channel forming regions decrease as the position approaches an interface where the channel forming region and a gate insulating film are in contact with each other.
According to another aspect of the invention, there is provided a manufacturing method of a semiconductor device including a plurality of bottom-gate TFTs formed on a substrate having an insulating surface, comprising the steps of: forming an amorphous silicon film; irradiating the amorphous silicon film with laser light or strong light having intensity equivalent to that of the laser light, to thereby convert the amorphous silicon film into a crystalline silicon film; adding an impurity element for a threshold voltage control to all or part of the crystalline silicon film; and activating the impurity element.
According to a further aspect of the invention, there is provided a manufacturing method of a semiconductor device including a plurality of bottom-gate TFTs formed on a substrate having an insulating surface, comprising the steps of forming an amorphous silicon film; adding an impurity element for a threshold voltage control to all or part of the amorphous silicon film; and irradiating the amorphous silicon film with laser light or strong light having intensity equivalent to that of the laser light, to thereby convert the amorphous silicon film into a crystalline silicon film and, at the same time, activate the impurity element.
According to still another aspect of the invention, there is provided a manufacturing method of a semiconductor device including a plurality of bottom-gate TFTs formed on a substrate having an insulating surface, comprising the steps of forming an amorphous silicon film; holding adjacent to or adding to all or part of the amorphous silicon film a catalyst element for accelerating crystallization of the amorphous silicon film; performing a first heat treatment to convert all or part of the amorphous silicon film into a crystalline silicon film; adding an impurity element for a threshold voltage control selectively to the crystalline silicon film; introducing an element selected form Group 15 elements selectively into the crystalline silicon film; and performing a second heat treatment to move the catalyst element to a region where the element selected from Group 15 elements is introduced and have the catalyst element gettered there and, at the same time, activate the impurity element for a threshold voltage control.
According to another aspect of the invention, there is provided a manufacturing method of a semiconductor device including a plurality of bottom-gate TFTs formed on a substrate having an insulating surface, comprising the steps of: forming an amorphous silicon film; irradiating the amorphous silicon film with laser light or strong light having intensity equivalent to that of the laser light, to thereby convert the amorphous silicon film into a crystalline silicon film; adding an element selected form Group 15 elements to a region to become an NTFT after the crystalline silicon film is obtained; adding an element selected form Group 13 elements to a region to become a PTFT after the crystallin

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