Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-05-30
2001-04-10
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185180, C365S185280, C365S185290
Reexamination Certificate
active
06215698
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention.
The present invention relates to a Flash EPROM and, more particularly, to a Flash EPROM with byte-wide erasure.
2. Description of the Related Art.
A non-volatile memory cell is a semiconductor device that stores information even after power has been removed from the device. One type of non-volatile memory cell is known as a Flash electrically-programmable read-only-memory (EPROM) cell.
In operation, Flash EPROM cells are programmed and read in the same fashion as conventional UV erasable EPROM cells. On the other hand, Flash EPROM cells are erased in the same fashion as conventional electrically-erasable programmable read-only-memory (EEPROM) cells.
When arrays of Flash cells were initially introduced commercially, the erase operation was typically limited to bulk erasure such that all of the cells in an array are erased at the same time. Since then, Flash EPROM arrays have been disclosed which teach row and byte-wide erasure.
FIG. 1
shows a schematic diagram that illustrates a portion of a conventional byte-erasable Flash EPROM
100
. As shown in
FIG. 1
, Flash EPROM
100
includes a number of Flash EPROM memory cells
110
that are arranged in rows and columns.
Each row of memory cells is broken into a number of byte-wide segments
120
. For example, the first row is broken into bytes
1
and
3
, while the second row is broken into bytes
2
and
4
. In addition, each row of memory cells has an adjacent row of memory cells that share a common source line segment
112
.
Each memory cell
110
, in turn, has a source region S connected to a common source line segment
112
, a drain region D, and a channel region that is defined between the source region S and drain region D. Further, each memory cell
110
has a floating gate that is formed over, and insulated from, the channel region, and a control gate that is formed over, and insulated from, the floating gate.
As further shown in
FIG. 1
, Flash EPROM
100
also includes a number of source access transistors
122
that are arranged in rows and columns so that a source access transistor
122
corresponds with each byte-wide segment
120
. Each source access transistor
122
has a source, a gate, and a drain connected to the common source line segment
112
that is connected to each source region S in the corresponding byte-wide segment.
Flash EPROM
100
additionally includes a series of word lines WL
1
-WLn that are arranged in rows so that each word line WL has both a corresponding row of memory cells
110
, and a corresponding row of source access transistors
122
. Each word line WL is connected to the control gate of each memory cell
110
in the corresponding row of memory cells
110
, and to the gate of each source access transistor
122
in the corresponding row of source access transistors
122
.
Further, Flash EPROM
100
also includes a series of bit lines BL
0
-BLm and a series of source lines SL
0
-SLr. Bit lines BL
0
-BLm are arranged in columns so that each bit line BL has a corresponding column of memory cells
110
. In addition, each bit line BL is connected to the drain of each memory cell in the corresponding column of memory cells
110
.
Source lines SL
0
-SLr are arranged in columns so that each source line SL has a corresponding column of source access transistors
122
. In addition, each source line SL is connected to the source of each source access transistor
122
in the corresponding column of memory cells
110
.
Thus,
FIG. 1
shows a schematic representation of four bytes of data: bytes
1
and
3
which are segments of the first row and thereby share the same word line WL
1
, and bytes
2
and
4
which are segments of the second row and thereby share the same word line WLn. Further, bytes
1
and
2
share the same bit lines BL
0
-BL
7
and the same source line SL
0
, while bytes
3
and
4
share the same bit lines BL
8
-BLm and the same source line SLr.
In operation, memory cells
110
are programmed row by row via channel hot electron (CHE) injection by placing a programming voltage on the word line WL that corresponds with the row of cells to be programmed. For example, if the first row of cells is to be programmed, then the programming voltage is placed on word line WL
1
.
In addition, a bit line voltage is placed on each of the bit lines BL
0
-BLm that are connected to a to-be-programmed memory cell
110
. For example, if only memory cell
1
-
1
in byte
1
is to be programmed, then the bit line voltage is placed on bit line BL
0
. The remaining bit lines, BL
1
-BLm in the above example, along with the remaining word lines WL
2
-WLn, are connected to ground. Further, ground is placed on all of the source lines SL
0
-SLr.
Memory cells
110
are read row by row by placing a read voltage on the word line WL that corresponds with the row of cells to be read. For example, if the first row of cells is to be read, then the read voltage is placed on word line WL
1
.
In addition, the bit line voltage is placed on each of the bit lines BL
0
-BLm that are connected to the memory cells
110
in the row of cells to be read. For example, if the first row of cells is to be read, then, then the bit line voltage is placed on bit lines BL
0
-BLm. The remaining word lines WLn are connected to ground. Further, ground is placed on all of the source lines SL
0
-SLr.
Memory cells
110
are erased by placing ground on the word line WL that corresponds with the segment of cells to be erased, and a positive voltage on the word line WL that corresponds with the adjacent segment of cells that share the same common source line segment
112
. For example, if byte
1
in the first row of cells is to be erased, then ground is placed on word line WL
1
, and the positive voltage is placed on WL
2
.
In addition, a high positive source voltage is placed on the source line SL that corresponds with the source access transistor
122
that is connected to the segment of cells to be erased. For example, if byte
1
is to be erased, then the high positive source line voltage is placed on source line SL
0
. The remaining source lines SLr, along with the remaining word lines WL
3
-WLn are connected to ground. Further, each of the bit lines BL
0
-BLm is floated.
Under these bias conditions, ground is applied to word line WL
1
and the high positive source voltage is applied to the sources of the memory cells in byte
1
via the source access transistor
122
in the adjacent row and source line SL
0
. The voltages on the word line and the sources set up an electric field that causes electrons to tunnel from the floating gate to the source region in each memory cell in byte
1
.
Although the above-described structure of Flash EPROM
100
provides byte-wide erasure, there is a need for alternative structures which can also provide byte-wide erasure.
SUMMARY OF THE INVENTION
The present invention provides a Flash electrically-programmable read-only-memory (EPROM) that allows byte-wide erasure. Bytes of cells are individually erasable by breaking each row of memory cells into byte-wide segments of memory cells, and utilizing a source access transistor with each segment of memory cells to control the source voltage on each segment of memory cells.
The Flash EPROM of the present invention includes a plurality of memory cells that arranged in rows and columns. Each row of memory cells is broken into a plurality of segments where each segment has a plurality of memory cells. Each memory cell, in turn, has a control gate.
The Flash EPROM also includes a plurality of source access transistors that arranged in rows and columns so that each source access transistor has a corresponding segment. Each source access transistor has an access gate.
In addition, a series of word lines are arranged in rows so that each word line has a corresponding row of memory cells. Each word line is connected to the control gate of each memory cell in the corresponding row of memory cells.
Further, a series of access lines are arranged in rows so that each access line has a corresponding row of source access
Bergemont Albert
Haggag Hosam
Dinh Son T.
National Semiconductor Corporation
Pillsbury & Winthrop LLP
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