Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
1998-11-06
2001-05-08
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S737000, C257S786000
Reexamination Certificate
active
06229218
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention generally relates to methods and devices for applying solder to workpieces and more particularly to a method and an apparatus for interconnecting electronic parts requiring the mating of dissimilar package footprints.
2. Background
The evolution of certain component parts employed in the manufacture of electronic assemblies is sometimes more rapid than the evolution of the printed circuit board (PCB) designs. For example if a surface mount component is upgraded from a quad flat pack (QFP) package format to a ball grid array (BGA) format it becomes necessary to redesign an entire PCB. The costs associated with the redesign of an entire PCB may be prohibitive, particularly in applications or manufactured devices having low count runs. Additionally, time may be lost and profits foregone while PCBs are redesigned and retooled to accommodate the evolution of a single component part. Additionally, if there is a large installed user base, it can make field upgrades cost prohibitive.
Potential solutions to this problem may include the use of surface mount socketing devices or the direct attachment of component parts having new or evolved configurations by traditional means of surface mounting and/or manual soldering methods. Others may attach fragile leadframes to the PCB to provide the interconnect method. However, these methods are often labor intensive and typically do not provide high yields. Additionally, these solutions may provide a visually unattractive device or they may be fragile and prone to defect.
Components continue, and will continue to be miniaturized and new and smaller package styles will be developed. As new package styles are developed and adopted by the industry, often it becomes harder and harder to purchase components in the older package styles. Sometimes, the older package styles go End Of Life (EOL) and are no longer produced.
This is not only a problem in manufacturing but also applies to repairing product in the field. When an obsolete part fails it is often necessary to simply replace the entire product as it is too expensive to modify in the field to accept an equivalent part.
What is needed is an efficient way to adapt a new part package to fit onto an existing PCB without redesigning the PCB layout.
SUMMARY OF THE INVENTION
According to one embodiment of the present invention an interconnect device for connecting an electronic package, whether it be a single chip or a multi-component device, to a primary substrate requiring the mating of dissimilar or mismatched solder patterns includes a secondary substrate having a first face and a second face. The first face of the secondary substrate may include a first pattern of conductive lands formed on the first face corresponding to a plurality of conductive leads of an electronic package. The second face of the secondary substrate includes a second pattern of conductive lands corresponding to a plurality of conductive lands formed on the primary substrate. The first pattern of conductive lands formed on the first face is electrically connected to the second pattern of conductive lands formed on the second face via surface and internal conductive paths. Lead-less solder ball solder methods are used to connect the electronic device to the secondary substrate and to connect the secondary substrate to the primary substrate.
The present invention also includes a method for connecting an electronic part to a primary substrate requiring the mating of dissimilar solder patterns. The method uses an interconnect device which has a first surface including a pattern of connection sites to receive the electronic part, a second surface which has a pattern of connection sites to match the connection sites on the primary substrate and a series of connections interconnecting the connection sites of the first and second patterns. The existing pattern of lands on the primary substrate is not altered, thus there is no need to re-work the layout of the primary substrate or PCB. However, the configuration of the individual lands within the existing pattern of lands is altered by masking off selective portions of the lands during manufacture of the PCB.
In one embodiment of the invention, the secondary substrate is formed of any dielectric material, however the most commonly used is FR-4 with a glass transition temperature (T
g
) of approximately 180° C. This provides a thermally and electrically efficient platform for the construction of such devices. A solder masking process is employed to achieve a reduced surface area of the lands on the original PCB. Advantageously, alternating ends of adjacent lands are masked resulting in increased spacing between solder sites to inhibit bridging of solder between lands and thereby allowing fine pitch package styles to be soldered using solder ball reflow techniques. This also inhibits the possibility of producing low volume solder joints due to the solder reflowing across the entire area of the previous land site. This method allows one to keep existing tooling and PCB designs and still use the standard preformed solder spheres such as those developed by Kester solder. The resulting conductive land array provides adequate clearance to use Eutectic (63% tin−37% lead) solder spheres which have an average melting temperature of 180° C.
Preformed solder spheres may be placed on the patterns of conductive lands formed on the faces of the secondary substrate utilizing a variety of methods including hand placement, the use of mechanical equipment to individually place sphere pre-forms onto a fluxed or solder printed land, the use of a paper array which has pre-formed solder spheres impregnated in the paper matrix which corresponds to the pattern of lands, or high volume placement using a stenciling process.
This secondary substrate can have either the traditional round sphere lands or attachment sites or rectangular lands or attachment sites. This improves the flexibility of the entire integration and provides a standoff height which increases long-term reliability of not only the component but also the PCB assembly as a whole.
One advantage of the present invention is that a user can migrate from one component package style to another without re-designing the existing PCB, and still maintain high assembly yields. This design provides a superior platform for attachment to a PCB over leaded or lead-less chip carrier designs because of increased component to board clearance, robustness of the package, and increased pitch of the connections which decreases the occurrence of solder bridging. The apparatus and method of the present invention not only reduce costs but also increase the reliability of the resulting manufactured parts and employ current methods to solve the interface problem.
Additional advantages and novel features of the invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following, or may be learned by practice of the invention. The advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 5834848 (1999-10-01), Iwasaki
patent: 5973930 (1999-10-01), Ikeda et al.
Casey William J.
Heidelberg Andrew J.
Skinner Daniel C.
Holland Joseph W.
MCMS Inc.
Potter Roy
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