Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1998-09-01
2001-03-27
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C365S185030
Reexamination Certificate
active
06209113
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods and apparatus for performing error correction on data read from memory systems (preferably integrated flash memory circuits) which are “multistate” systems in the sense that each memory cell has more than two states (each state determining a different data value). More particularly, the invention is a method and apparatus for performing error correction on data read from a multistate memory system (preferably a flash memory circuit), in which the data read from each memory cell is encoded so that in response to detection of an error in the encoded data from one memory cell, the error is corrected by changing one bit of the encoded data.
2. Description of Related Art
Throughout the specification, including in the claims, the term “connected” is used (in the context of an electronic component being “connected” to another electronic component) in a broad sense to denote that the components are electrically or electromagnetically coupled with sufficient strength under the circumstances. It is not used in a narrow sense requiring that an electrically conducting element is physically connected between the two components.
Multistate memory systems are becoming increasingly commercially important. Such systems include one or more arrays of memory elements, with each memory element having more than two states (each state determining a different data value). The synonymous terms “cell” of a memory array and “element” of a memory array are used interchangeably herein. A flash EEPROM multistate memory system is described in U.S. Pat. No. 5,043,940, issued Aug. 27, 1991, and an electrically alterable non-volatile multistate memory system is described in U.S. Pat. No. 5,394,362 issued Feb. 28, 1995.
Throughout the specification, including in the claims, the term “bit” is used herein to denote the data stored in one memory element of a memory system (which can be either a multistate memory system or a two-state memory system). In the special case of a two-state memory system, each element stores a “binary” bit (whose value can be denoted by the binary representation “0” or “1”). In the special case of a four-state memory system, each element stores a bit having one of four possible values (which can be denoted by the binary representations “00”, “01”, “10”, and “11”).
It has been proposed to design nonvolatile memory chips (integrated circuits) as multistate memory systems, so each memory element (“cell”) of such a system has more than two states. Since analog values can be stored on the floating gate of a typical nonvolatile memory cell (e.g., a flash memory cell), it is possible to define more than two states for each such cell and hence reduce the area per stored bit for each cell. It is predictable that improved technology will continue to reduce the practical size of memory cells and that in some designs, a cell will be implemented as an intersection of two poly elements.
A problem with multistate storage is that by putting more states on each cell, the effective voltage range for each state becomes smaller. E.g., for a 5 volt window of operation on a floating gate (this window being determined by the particular circuitry used to “read” the cell), one can define the midpoint to be the boundary (or threshold) between the two states. Thus, a voltage stored on the gate determines a first state (corresponding to a first binary bit) if it is detected to be in the upper 2.5 volts of the window, and a voltage stored on the gate determines a second state (corresponding to a second binary bit) if it is detected to be in the lower 2.5 volts of the window. However, if a “read” circuit having the same window is used to distinguish between four states of the floating gate, each state corresponds to only 1.25 volts of the window. So, the noise margin for each state (e.g., the maximum range of voltage change, from the center of the window portion for the state, before the state is no longer valid) is reduced by a factor of two when the floating gate is used as four-state cell rather than a two-state cell.
There is also a limit to the precision with which circuitry can store an analog value on the floating gate of a nonvolatile memory cell. With today's architectures and high densities, cells across a nonvolatile memory array do not all behave identically. For these reasons, conventional circuitry for performing a program or erase of the bits in a nonvolatile memory array is typically designed to perform the task in an algorithmic manner in which the circuitry asserts an appropriate voltage level to a cell, then interrogates the value of the cell, and if the cell has not yet developed a sufficient margin, the circuitry again asserts an appropriate voltage level thereto. Using such circuitry, incremental varying of the voltage on a floating gate of each cell is not difficult, so that multistate storage becomes feasible.
To reduce the cost of nonvolatile memory systems, defective memory arrays can be tolerated and error correction employed to regain the data integrity. If one allows memory arrays having a few bad elements to be used in a system, the price of the system can be substantially reduced since much greater manufacturing yield can be attained. In order to enable the reader to more readily appreciate the present invention, we next describe (with reference to
FIGS. 1 and 2
) a nonvolatile memory system having conventional design, which includes conventional error detection and correction circuitry, including ECC encoder
40
, ECC decoder
41
, error correction unit
42
, and syndrome decoder
43
(of FIG.
1
).
Nonvolatile memory chip
3
of
FIG. 1
includes an array
16
of nonvolatile memory cells, each cell comprising a transistor having a floating gate capable of semipermanent charge storage. The current drawn by each cell depends on the amount of charge stored on the corresponding floating gate. Thus, the charge stored on each floating gate determines a data value that is stored “semipermanently” in the corresponding cell.
In one particularly useful implementation of memory chip
3
, each cell of array
16
comprises a flash memory device (a transistor). The charge stored on the floating gate of each flash memory device (and thus the data value stored by each cell) is erasable by appropriately changing the voltage applied to the gate and source (in a well known manner).
As shown in
FIG. 1
(a simplified block diagram of nonvolatile memory chip
3
), chip
3
includes a host interface
10
(including an I/O buffer for input data received from an external device and output data to be asserted to an external device), an address buffer
30
, row decoder circuit (X address decoder)
12
, column multiplexer circuit (Y multiplexer)
14
, memory array
16
(comprising columns of nonvolatile memory cells, such as column
16
A), sense amplifier circuit
15
, and control unit
29
.
Address bits received at interface
10
from an external device are asserted to address buffer
30
. In response to a set of address bits A
0
through Ap received from an external device, address bits A
0
through An are asserted from buffer
30
to X decoder
12
, and address bits An+1 through Ap are asserted from buffer
30
to Y multiplexer
14
.
Chip
3
executes a write operation by receiving data bits (to be written to memory array
16
) from an external device at interface
10
, buffering the data in interface
10
, including ECC check bits with the data (in unit
40
), and then writing the data (and ECC check bits) to the appropriate memory cells of array
16
. Chip
3
can also be controlled to execute a read operation in which data that has been read from array
16
undergoes error detection and correction in units
41
,
42
, and
43
, and the corrected data is then buffered in interface
10
and asserted to the external device.
Since the cells of array
16
are flash memory cells, data is typically written to cells which have been erased. Each cell is either allowed to remain in the erased state, or is prog
Baker Stephen M.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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