Tristate structures for programmable logic devices

Details Tristate structures for programmable logic devices Tristate structures for programmable logic devices

1998-10-09

2001-05-29

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S058000

Reexamination Certificate

active

06239613

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the field of programmable logic integrated circuits. More specifically, the present invention provides an enhanced programmable logic architecture, improving upon the composition, configuration, and arrangements of logic array blocks (LABs) and logic elements (LEs) and also the interconnections between these logic array blocks and logic elements.
Programmable Logic Devices (PLDs) are well known to those in the electronic art. Such programmable logic devices are commonly referred as PALs (Programmable Array Logic), PLAs (Programmable Logic Arrays), FPLAs (Field Programmable Logic Arrays), PLDs (Programmable Logic Devices), EPLDs (Erasable Programmable Logic Devices), EEPLDs (Electrically Erasable Programmable Logic Devices), LCAs (Logic Cell Arrays), FPGAs (Field Programmable Gate Arrays), and the like. Such devices are used in a wide array of applications where it is desirable to program standard, off-the-shelf devices for a specific application. Such devices include, for example, the well-known, Classic™, and MAX® 5000, MAX® 7000, and FLEX® 8000 EPLDs made by Altera Corporation.
PLDs are generally known in which many LABs are provided in a two-dimensional array. Further, PLDs have an array of intersecting signal conductors for programmably selecting and conducting logic signals to, from, and between the LABs. LABs contain a number of individual programmable logic elements (LEs) which provide relatively elementary logic functions such as NAND, NOR, and exclusive OR.
Resulting from the continued scaling and shrinking of semiconductor device geometries which are used to form integrated circuits (also known as “chips”), integrated circuits have progressively become smaller and denser. For programmable logic, it becomes possible to put greater numbers of programmable logic elements onto one integrated circuit. Furthermore, as the number of elements increases, it becomes increasingly important to improve the techniques and architectures used for interconnecting the elements and routing signals between the logic blocks.
While such devices have met with substantial success, such devices also meet with certain limitations, especially in situations in which the provision of more complex logic modules and additional or alternative types of interconnections between the logic modules would have benefits sufficient to justify the additional circuitry and programming complexity. There is also a continuing demand for logic devices with larger capacity. This produces a need to implement logic functions more efficiently, with better performance, and to make better use of the portion of the device which is devoted to interconnecting individual logic modules.
As can be seen, an improved programmable logic device architecture is needed, especially a programmable logic architecture which provides for additional logical resources such as tristate structures for improving the interconnection resources between the logic elements.
SUMMARY OF THE INVENTION
The present invention is a programmable logic architecture. The architecture provides for the implementation of tristate structures in programmable logic devices.
In one embodiment of the present invention, a plurality of logic elements are coupled through tristate switches to a tristate bus. From the tristate bus, the signals may be coupled through tristate drivers to a global interconnect structure, where the signals may be programmably coupled to LABs and LEs. OE generation circuits control the operation of the tristate switches. Logical signals from LABs and LEs may be programmably coupled through the global interconnect structure to the OE generation circuits to control whether the tristate switches are enabled or disabled. For example, LEs and LABs may logically control the tristate switches by coupling through tristate drivers and the global interconnect structure to the OE generation circuits. The enabled and disabled states of the tristate switches may also be programmably controlled by way of programmable cells.
In another embodiment of the present invention, the logic elements are coupled through tristate drivers to the global interconnect. The tristate drivers are controlled by a tristate control, which may be integrated into the logic of a LAB. From the tristate control, the tristate drivers may be logically controlled by signals on the programmable and global interconnect. Furthermore, the tristate drivers may also be programmably controlled by way of programmable cells. A plurality of tristate drivers may be coupled to share the same global interconnect line.
The tristate driver of the present invention may buffer and drive an input signal to an output line. This tristate driver may provide sufficient drive capability for driving a programmable interconnect conductor, which may be relatively heavily loaded. The tristate driver may be programmably and logically controlled. More specifically, the tristate driver may be programmably disabled, where its output will be tristated regardless of the states of logical inputs. When programmably enabled, the tristate driver output will be tristated or enabled depending on the states of the logical inputs. When logically and programmably enabled, the input line will be driven to the output line.
The architecture of the present invention provides greater utilization and flexibility in using the programmable and global interconnect structures of the programmable logic device. The architecture also provides greater utilization and flexibility in using the logic elements and other programmable resources. Furthermore, the programmable logic functions in this architecture may be dynamically and logically reconfigured, without the need to reprogram programmable cells. Further, the architecture of the present invention provides better performance and operating characteristics, including improved transient response.
The tristate structures of the present invention are useful for communication between multiple blocks of logic which share a common bus. More specifically, in an embodiment, the present invention includes: logic blocks which need to communicate with one another; tristate devices which drive a common tristate bus; a common signal bus, which may or may not be part of the tristate bus, that facilitates communication between the logic blocks; logic to control the enabling and disabling of the tristate devices; and, a signal path for coupling the tristate bus to the signal bus.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.


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