Level-shift circuit for driving word lines of negative gate eras

Details Level-shift circuit for driving word lines of negative gate eras Level-shift circuit for driving word lines of negative gate eras

1995-08-04

1998-10-20

Santamauro, Jon

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 68, 326 83, 36523006, H03K 190185

Patent

active

058252053

ABSTRACT:
A level-shift circuit includes first and second inverting circuits, first and second inverting circuits each operated with a voltage between a potential higher than a power supply potential and a potential lower than the ground potential used as a power supply voltage. The input terminal of the first inverting circuit is connected to the output terminal of the second inverting circuit, and the output terminal of the first inverting circuit is connected to the input terminal of the second inverting circuit. Current paths of first and second MOS transistors are serially connected between the input terminal of the first inverting circuit and the ground and the gate of the second transistor is supplied with an input signal whose high level is set at the power supply potential and whose low level is set at the ground potential. Current paths of third and fourth MOS transistors are serially connected between the input terminal of the second inverting circuit and the ground. A first inverter converts the low level of an erasing signal to a potential lower than the ground potential and supplies the level-converted signal to the gates of the first and third transistors. A second inverter is supplied with the input signal and supplies an inverted signal of the input signal to the gate of the fourth MOS transistor. The level-shifted output is output from at least one of the output terminal of the first inverting circuit and the output terminal of the second inverting circuit.

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