Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1995-06-07
2001-03-13
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S390000, C257S397000, C257S398000
Reexamination Certificate
active
06201277
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to non-volatile memories, and more specifically to electrically programmable read-only memories.
BACKGROUND OF THE INVENTION
An electrically programmable read-only memory (EPROM) can be electrically programmed to permanently store data. EPROMs rely on a charge tunneling phenomenon to permanently store a charge in an electrical conductor of each cell. Avalanche and Fowler-Nordheim effects are examples of the tunneling phenomenon. Essentially, an EPROM is programmed by applying certain voltages thereto, sufficient to draw electron charges through a thin insulator and become trapped in a conductive material, such as polycrystalline silicon or silicon nitride. The voltages applied to the cell for reading the contents thereof are insufficient to release the trapped charges, and thus, once electrically programmed, the cell retains the information for a long period of time.
In semiconductor memory technology, there is a constant effort to construct devices with higher circuit densities to accommodate more cells per unit of wafer area. As technology increases and device areas become smaller, the area required to isolate cells from each other makes up a larger percentage of the total area required by an EPROM. Thus, there is a need to reduce the area required to isolate EPROM cells from each other.
SUMMARY OF THE INVENTION
A programmable memory device having a plurality of memory cell rows is disclosed. Each memory cell row comprises a plurality of floating gates separated from a surface of semiconductor body by a gate dielectric and a plurality of slot trenches for isolating memory cells of the memory cell row from each other. Each of the slot trenches extends below the surface of the semiconductor body between adjacent floating gates. Each memory cell row also comprises a control gate extending over the floating gates and a portion of each of the slot trenches.
An advantage of the invention is providing a programmable memory that allows a higher packing density.
A further advantage of the invention is providing an isolation scheme for a programmable memory that avoids the prior art problems associated with moat encroachment.
A further advantage of the invention is providing an isolation scheme for a programmable memory that avoids Kooi effects (undesired silicon nitride growth).
A further advantage of the invention is providing an isolation scheme for a programmable memory that produces reproducible line widths.
These and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings and claims.
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Brady W. James
Hoel Carlton H.
Ngo Ngan V.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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