Reflow of low melt solder tip C4's

Details Reflow of low melt solder tip C4's Reflow of low melt solder tip C4's

1999-07-21

2001-07-10

Wong, Don (Department: 2821)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257S772000

Reexamination Certificate

active

06258703

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the reflow of low temperature solder interconnects, especially in microelectronics fabrication.
BACKGROUND OF THE INVENTION
Controlled Collapse Chip Connection (C
4
) is an advanced interconnect technology for microelectronic chip packaging. C
4
is also known as “flip chip,” “solder bump” and “solder balls.”
The basic idea of C
4
is to connect chips, chip packages or other such units by means of solder bumps partially collapsed between the surfaces of two units. Each unit has a pad pattern which corresponds to a mirror image pattern of the other. The bumps of electrically conductive solder bridge the gap between respective pairs of metal pads on the units being connected. As the units are brought together, the solder bumps on the pads of the first unit are pressed against the corresponding conductive pads on the second unit, resulting in the partial collapse of the solder bump and formation of an interconnect between respective pads. This allows for the simultaneous formation of all interconnects between the units in a single step, in spite of slight variations in the surfaces of the units being joined.
In C
4
, the solder bumps are formed directly on the metal pads of one unit. The pads are electrically isolated from each other and other components by the insulating substrate that surrounds each pad. The substrate may be un-doped silicon or some other material. The bottom of each pad is in contact with a via, forming electrical continuity with the chip circuitry.
A major application of C
4
is in joining semiconductor integrated circuit chips to chip packages. Integrated circuits are fabricated from semiconductor wafers in an array of repeat patterns, then diced into individual chips in order to minimize the processing cost per chip. Once separated into individual units, the chips are then assembled into packages large enough to handle. C
4
bumps are placed on the chips prior to dicing, incorporating the benefits of wafer scale processing.
Chip sizes are continually shrinking, while circuit densities and I/O counts continue to increase, in order to enhance performance and reduce costs. These trends place higher demands on interconnects, making traditional bonding methods such as wire bonding and tape automated bonding (TAB) very difficult. C
4
allows for very high density I/O with area array distribution as compared to peripheral contacts in TAB and wire bonding.
C
4
solder bumps serve two functions; first, they act as electrical interconnects and second, they act to form a physical bond between the semiconductor chip and package. This demands a very precise placement of each C
4
as well as uniform control of solder volumes.
One method of forming solder bumps is by vacuum deposition. A specially made mask with high precision vias is placed over the wafer for locating the solder bumps. The entire assembly is then placed into a vacuum chamber where solder is evaporated through the mask to form solder bumps on the wafer. This deposition process is non-selective, thereby solder deposits throughout the chamber as well as on the mask. During deposition, the wafer and mask are heated, therefore careful selection of mask material to match the coefficient of thermal (CTE) expansion of the wafer is needed. However, for this reason, the evaporation technique has limited extendibility to larger wafers.
An alternative technique for making solder bumps is electrodeposition, also called electrochemical plating or electroplating. This method also uses a mask to form solder bumps only at selected sites, but is vastly different than the evaporation technique.
Electrodeposition of solder bumps requires a continuous electrically conductive “seed layer”
14
adhered to the insulating substrate. The seed layer
14
function is to carry current necessary for electroplating the solder.
FIG. 1A
, labeled “prior art,” shows a wafer substrate
10
whose surface is overlaid with a conductive layer
11
of either chromium (Cr) or a titanium tungsten alloy (Ti—W). Metal layer
11
will function as part of the seed layer for electrodepositing solder bumps. On top of layer
11
is deposited a thin “phased” layer
12
of 50% chromium and 50% copper (Cr—Cu). Finally, a third layer
13
of pure copper is deposited over the entire wafer surface. The Cr or Ti—W, Cr—Cu and Cu layers are of comparable thickness. Once seed layer
14
is deposited, the wafer is coated with photoresist, patterned and then exposed. The unexposed regions can then be developed or dissolved away to leave behind the cured photoresist as a mask
16
shown in FIG.
1
A. Photoresist mask
16
forms the desired pattern of holes or vias across the wafer.
The next step is the electrodeposition of solder into the vias of the mask
16
. All vias are filled simultaneously with the desired volume of solder during the deposition process. An electroplated solder bump
18
is shown in FIG.
1
A. Once the solder bumps
18
are formed, photoresist mask
16
is removed leaving behind the solder bumps
18
and the continuous seed layer
14
.
In order to electrically isolate solder bumps
18
, it is necessary to remove the seed layer
14
between solder bumps
18
. This is accomplished by etching away layers
11
-
13
with chemical or electrolytic action, in either case the solder bump
18
protects the layers
11
-
13
under it.
FIG. 1B
shows the seed layers
11
-
13
removed to leave the solder bumps electrically isolated but mechanically fixed to substrate
10
. U.S. Pat. No. 5,486,282 (which is incorporated herein by reference) discloses an invention related to the selective removal of Cu and phased Cr—Cu by electroetching. U.S. Pat. Nos. 5,462,638 and 5,800,726 (which are incorporated herein by reference) disclose inventions related to the removal of a Ti—W alloy layer by chemical etching.
FIG. 1C
shows solder ball
18
′, formed by melting or reflowing the solder bump
18
of
FIGS. 1A-1B
. At this stage the solder ball is ready for joining.
Solder alloys used in C
4
interconnects generally consist of lead (Pb) and tin (Sn). One characteristic used to select the solder alloy is the melting temperature. Conventionally chips were joined to multi-layer ceramic (MLC) substrates which could withstand temperatures greater than 350° C. However, there is a growing need to attach chips to organic packages, as well as direct chip attach (DCA) to organic boards such as FR
4
boards, which can generally only withstand temperatures less than 300° C. A Pb—Sn alloy used for the high temperature application may contain 97% Pb and 3% Sn by weight which melts at 353° C., and for the low temperature application may contain 37% Pb and 63% Sn by weight (eutectic PbSn) which melts at 183° C.
During the reflow of solder bump
18
to form solder ball
18
′, Sn present in the solder reacts with the upper most Cu region of the third layer
13
of Cu, to form an intermetallic (Cu
x
, Sn
y
,) where x is 6 and y is 5 or where x is 3 and y is 1. This intermetallic layer forms a strong bond between the solder ball
18
′ and the third layer
13
of Cu. In the high temperature application, with minimal Sn present (3 Wt. %), the degree of intermetallic formation is self limiting. However, in the low temperature application, with eutectic PbSn solder (63 Wt. % Sn), the excessive amount of Sn can react with and consume the underlying third layer
13
of Cu, degrading the solder-seed layer interface.
One method of forming a low temperature C
4
structure is by capping a high temperature C
4
bump with low temperature eutectic Pb—Sn solder, such as described in U.S. Ser. No. 08/710,992 filed Sep. 25, 1996 by Berger et al. entitled “Method for Making Interconnect for Low Temperature Chip Attachment” now U.S. Pat. No. 6,127,735 which issued Oct. 3, 2000 and assigned to assignee herein which is incorporated herein by reference. However, this method does not address the issue of low temperature solder wicking down around the high temperature C
4
structure and attacking seed layer
14
from the side or expo

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