Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-08-26
2001-09-25
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S321000
Reexamination Certificate
active
06294808
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention pertains in general to a non-volatile memory device and, more particularly, to a non-volatile memory device with field-enhancing floating gate and a method for forming the same.
2. Description of the Related Art
A non-volatile memory device may be programmed through Fowler-Nordheim tunneling or “hot” electron injection. Hot electrons are those with high kinetic energy and may be acquired through a locally-enhanced electric field. Some electrons in the channel region of the device substrate may be induced through either Fowler-Nordheim tunneling or hot electron injection to penetrate a dielectric layer that separates the substrate from a floating gate. When the electrons have penetrated the dielectric layer and stored at the floating gate, the device is said to be programmed. The stored electrons may be removed from the floating gate through a control gate, or select gate, that overlaps the floating gate. The floating gate and the control gate are separated by a second dielectric layer. With Fowler-Nordheim tunneling, the electrons stored in the floating gate may be induced to tunnel through the second dielectric layer to the control gate. After the stored electrons are removed from the floating gate, the device is said to be erased.
U.S. Pat. No. 5,278,087 (“the '087 patent”) discloses a method of making a single transistor non-volatile electrically alterable semiconductor memory device with a re-crystallized floating gate. U.S. Pat. No. 5,242,848 (“the '848 patent”) discloses a self-aligned method of making a split gate single transistor non-volatile electrically alterable semiconductor memory device.
FIG. 1
is a cross-sectional side view of a single transistor non-volatile electrically alterable memory cell disclosed in the '087 and the '848 patents. Referring to
FIG. 1
, a memory cell
10
includes a semiconductor substrate
12
. Substrate
12
includes a drain region
16
, a source region
14
and a channel region
18
therebetween. Disposed over substrate
12
is a first layer
20
of dielectric material, which may be composed of silicon dioxide, silicon nitride, or silicon oxynitride. A polysilicon floating gate
22
is disposed over first layer
20
and overlaps a portion of channel region
18
and a portion of source region
14
. A second dielectric layer
25
has a first section
24
disposed over floating gate
22
and a second section
26
adjacent to floating gate
22
. Layer
25
may be composed of silicon dioxide, silicon nitride, or silicon oxynitride.
Cell
10
also includes a control gate
29
having a first portion
28
and a second portion
30
. First portion
28
is disposed over first portion
24
of layer
25
and second portion
30
is disposed over layer
20
and contiguous with second portion
26
of layer
25
. Second portion
30
also extends over a portion of drain region
16
and a portion of channel region
18
.
Both the '087 and the '848 patents describe that cell
10
may be programmed by applying a ground potential to drain region
16
, a threshold voltage to control gate
29
, and a positive high voltage on the order of 12 volts to source region
14
. Under such a bias condition, electrons from drain region
16
flow towards source region
14
through channel region
18
. A locally generated electrical field in channel region
18
causes some of the electrons to become “hot”, i.e., acquire kinetic energy. For those having acquired enough kinetic energy, some will inject into floating gate
22
through layer
20
.
The '087 and '848 patents also describe that the electrons stored in floating gate
22
after programming may be removed through Fowler-Nordheim tunneling. By applying 15 volts to control gate
29
and a ground potential to source region
14
and drain region
16
, the stored electrons will tunnel through layer
25
to control gate
29
and may be removed through control gate
29
. Electron tunneling is attributed to a locally enhanced field from floating gate
22
.
The '087 and the '848 patents are hereby incorporated by reference.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a non-volatile memory device with a field-enhancing floating gate and a method for forming the same that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structures and methods particularly pointed out in the written description and claims thereof, as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and broadly described, there is provided a non-volatile memory device that includes a semiconductor substrate, first and second spaced-apart regions in the substrate with a channel region therebetween, and a first dielectric layer disposed over the substrate. The device also includes a floating gate disposed over the first dielectric layer. The floating gate extends over a portion of the channel region and over a portion of the second spaced-apart region, and includes a top portion, a bottom portion and at least five sides wherein the bottom portion is contiguous with the first dielectric layer. The device further includes a second dielectric layer having a first and a second connected sections wherein the first dielectric section is contiguous with at least two of the five sides of the floating gate and the second dielectric section is disposed over and contiguous with the top portion of the floating gate, and a control gate that has a first section disposed over the first dielectric layer and contiguous with the second dielectric layer.
In one aspect of the invention, a voltage of between approximately 0 and 0.6 volts is applied to the first spaced-apart region, a voltage of approximately 11 volts is applied to the second spaced-apart region, and a threshold voltage is applied to the control gate to inject electrons from the channel region into the floating gate.
In another aspect, a ground potential is applied to the first spaced-apart region and the second spaced-apart region, and a voltage of approximately 14 volts is applied to the control gate to induce Fowler-Nordheim tunneling of electrons from the floating gate to the control gate.
Also in accordance with the invention, there is provided a non-volatile memory device having a substrate and a first dielectric layer disposed over the substrate. The device includes a floating gate disposed over the first dielectric layer, wherein the floating gate has a top portion, a bottom portion, and a protrusion. The device also includes a second dielectric layer disposed over the floating gate and a control gate disposed over the second dielectric layer. The protrusion of the floating gate creates an enhanced local field to induce Fowler-Nordheim tunneling of electrons from the floating gate to the control gate when a high voltage is applied to the control gate.
Further in accordance with the invention, there is provided a method for forming a non-volatile memory device that includes the steps of defining a substrate, forming a first layer of dielectric material over the substrate, depositing a first layer of polysilicon over the first layer of dielectric material, masking the first polysilicon layer to define a floating gate, and patterning the first polysilicon layer to form a floating gate. The method also includes the steps of masking the floating gate to define at least five sides of the floating gate that includes one protrusion, and patterning and forming the floating gate to form the at least five sides and the one protrusion. The method additionally includes the steps of forming a second layer of dielectric material over the floating ga
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Prenty Mark V.
Winbond Electronics Corporation
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