Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-09-30
2001-04-17
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S300000, C257S301000
Reexamination Certificate
active
06218693
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to an integrated circuit semiconductor device, and more particularly to a structure and a method for fabricating a new dynamic random access memory (DRAM) cell having a horizontally extending trench storage capacitor.
(2) Description of the Prior Art
Dynamic random access memory (DRAM) devices are used for storing digital information on arrays of memory cells in the form of charge stored on a capacitor. Each memory cell consists of a single access transistor and a single storage capacitor. The access transistors are usually N-channel field effect transistors (FETs) and are electrically connected by word lines to the peripheral address circuits. The storage capacitors are formed either by etching trenches in the substrate in each of the cell areas, commonly referred to as trench capacitors, or are formed over the access transistors in the cell areas by depositing and patterning conducting layers over the access transistors, and are commonly referred to as stacked capacitors. The capacitors make electrical contact to one of the two source/drain areas (node contact) of each FET, while bit lines make electrical contact to the other source/drain area of each FET. It is necessary that each capacitor lie within an area no larger than the size of the cell area in order to accommodate all the capacitors in the large array of cells used on the DRAM device.
It is becoming increasingly difficult to fabricate more memory cells on a DRAM device while limiting the overall DRAM device area to a practical size without decreasing the cell area. For example, after the year 2000 the number of memory cells is expected to reach 1 gigabit. Further, as the cell area decreases, the available area for the storage capacitor in each cell also decreases. This makes it difficult to maintain sufficient capacitance to provide the necessary signal-to-noise ratio. Also, the refresh cycle time necessary to maintain sufficient charge on these capacitors also decreases, resulting in DRAM devices with reduced performance (speed).
One method in the semiconductor industry of overcoming the above problems is to form DRAM devices having stacked capacitors. These types of capacitors extend vertically upward (z-direction) over the pass transistors and can be made with increased area in the z-direction while minimizing the area in the x-y directions, that is, along the substrate surface. The two basic types of stacked capacitor DRAM cells of the prior art are the Capacitor Under Bit line (CUB) structure shown in
FIG. 1
, and the Capacitor Over Bit line (COB) shown in FIG.
2
.
Shown in
FIG. 1
is a schematic cross-sectional view for the CUB structure. In this approach a field oxide (FOX) isolation, for example, a shallow trench isolation (STI)
12
, is formed in a silicon substrate
10
surrounding and electrically isolating the cell area. An FET is formed next by thermally growing a gate oxide
14
on the active device area in an oxidizing atmosphere, and then depositing and patterning a polysilicon or polycide layer
16
to form the FET gate electrode
16
. The FET lightly doped source/drain areas
17
are formed next by ion implantation, and an insulating layer
18
is deposited and anisotropically plasma etched back to form sidewall spacers
18
. Optionally source/drain contact areas
19
are then formed by using a second ion implantation to complete the FET. The stacked storage capacitors are formed next after depositing an InterLevel Dielectric Layer (ILD), that is an insulating layer
20
. Capacitor node contact holes, such as contact hole
2
in
FIG. 1
, are etched in layer
20
to one of the two source/drain areas
19
of each FET. (Only one of the many DRAM cells of the array of DRAM cells is depicted in
FIG. 1.
) The bottom capacitor electrode
22
making electrical contact
22
′ (node contact) in the contact hole
2
to the FET source/drain
19
is formed next by various means. For example, a single doped polysilicon layer
22
can be deposited and patterned to form the bottom electrode
22
for a block capacitor. Also, by including additional layers and process steps, crown-shaped capacitors, fin-shaped capacitors, and the like can be formed. The stacked capacitor is then completed by depositing a thin high-dielectric constant (high-k) interelectrode dielectric layer
24
and a top electrode
26
that is deposited and patterned. A second insulating layer
28
(InterMetal Dielectric (IMD) layer) is deposited to insulate the capacitor. Bit line contact holes, such as contact hole
4
in
FIG. 1
, are etched in layer
28
to the second FET source/drain area
19
. The bit lines
30
are then formed by depositing and patterning a first metal layer, such as an aluminium/copper alloy having a barrier layer such as a titanium/titanium nitride, to make electrical contact
30
′ to the second source/drain area
19
to complete the array of DRAM cells. Optionally the bit lines can be a polycide (metal silicide/polysilicon layer), such as tungsten silicide (WSi
2
) or titanium silicide (TiSi
2
).
Unfortunately, the topography can be quite rough and leveling and planarizing techniques are employed to provide a planar surface on which submicrometer structures (e.g., bit lines) can be reliably formed. These planar surfaces are needed to expose the distortion-free photoresist images (patterns) because of the shallow depth of focus (DOF) required for the high-resolution lithography. The planar surface is also required to avoid residue (rails, fences, etc.) at steep steps when the next level of conducting layers is anisotropically plasma etched. Another problem is the high aspect ratio (height/width) of the bit line contact holes that can result in high contact resistance, or even result in electrical opens (broken bit lines).
Another method of making DRAM cells with stacked capacitors is shown in the schematic cross-sectional view in FIG.
2
. These DRAM cells are referred to as Capacitor Over Bit line (COB), and are similar in fabrication to the CUB DRAM cells, and therefore the numbered elements are similarly labeled. However, in this COB structure, the bit lines
30
, having bit line contacts
30
′ in the bit line contact holes
4
in insulating layer
20
, are formed prior to forming the stacked capacitors. Although the bit line contact holes have reduced aspect ratios, the bit lines are usually formed from a lower electrical conductivity, high-melting-temperature material (e.g., doped polysilicon and silicides), since high-temperature processing is generally required to complete the stacked capacitors. However, the node contacts for the stacked capacitors require high-aspect-ratio node contact openings which are difficult to etch, and all the rough topography concerns of the CUB apply to the COB DRAM cell structure.
Another major concern in making stacked capacitors is that both the bit lines and capacitors are formed above the silicon surface. This is best illustrated in the schematic three-dimensional view of a COB DRAM cell in FIG.
3
. As the DRAM cell continues to decrease in size, it becomes increasingly difficult to built both the bit line and capacitor in the same plane above the silicon substrate surface while keeping sufficient spacing between the bit line and stacked capacitor.
FIG. 3
shows two COB DRAM cells having two adjacent crown capacitors
22
with a common bit line
30
fabricated up to the bottom electrodes
22
. The insulating layers
20
and
28
of
FIG. 2
are not shown to better depict the structure. As shown in
FIG. 3
, as the active device area
1
surrounded by the STI
12
becomes smaller to accommodate more memory cells on the DRAM device, the spacing between the bit line
30
and the stacked capacitor contacts
22
′ must be made smaller. This results in inadequate separations between the bit line and capacitor contacts which are formed in the same plane and can result in electrical shorts. Sometimes irregular shaped cell structures (twisted cell structures) are designed to maximize
Ackerman Stephen B.
Crane Sara
Nguyen Cuong Quang
Saile George O.
Vanguard International Semiconductor Corporation
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