Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2000-01-21
2001-04-10
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S203000
Reexamination Certificate
active
06215723
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having sequentially disabling activated word lines.
2. Description of the Related Art
When a semiconductor memory device is manufactured, the semiconductor memory device undergoes a burn-in stress test and a function test. The burn-in stress test ensures that the semiconductor memory device works under prescribed stress conditions, such as a boosted voltage applied to the semiconductor memory device. The function test is for testing whether the semiconductor memory device operates normally according to a predetermined product specification.
Generally, a method of simultaneously activating a plurality of word lines or sequentially activating a plurality of word lines is used to reduce the time required for the burn-in stress test or the function test. Then, the plurality of activated word lines are simultaneously disabled after the activation of the plurality of word lines. When the plurality of activated word lines are simultaneously disabled, precharge noise is generated during a process where the plurality of word lines are transited from a high level to a low level. The precharge noise can have a critical influence on operations of the semiconductor memory device.
Therefore, a need exists for a semiconductor memory device having function of sequentially disabling the activated word lines to prevent the precharge noise from occurring at the time of disabling the activated word lines.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device for preventing precharge noise from being generated in a process of disabling a plurality of activated word lines.
Accordingly, the present invention provides a semiconductor memory device having a plurality of memory cells and a plurality of word lines connected to the plurality of memory cells, comprising a predecoding unit, a row decoding and word line driving block, and a controller. The predecoding unit predecodes a row address received from the outside. The row decoding and word line driving block, which is connected to the predecoding unit and the plurality of word lines, decodes an output of the predecoding unit, selects some of the plurality of word lines, and activates selected word lines. The controller connected to the predecoding unit and the row decoding and word line driving block, receives the row address, the output of the predecoding unit, and at least one control signal, generates at least one output signal, and sequentially disables the activated word lines by enabling the at least one output signal in response to the row address and the output of the predecoding unit when the at least one control signal is enabled in a state where some of the plurality of word lines are activated. The at least one control signal may be a mode register set signal for controlling operating modes of the semiconductor memory device, and may have a voltage higher than a supply voltage of the semiconductor memory device.
The controller may include a first row decoding controller for generating first and second word line control signals by receiving the row address, the mode register set signal, the precharge signal, and an active signal, wherein the first row decoding controller enables the first and second word line control signals when the mode register set signal and the active signal are enabled in a state where the precharge signal is disabled, and disables the first and second word line control signals when the precharge signal is enabled; a second row decoding controller connected to the first row decoding controller, the predecoding unit, and the row decoding and word line driving block, for providing the row decoding word line driving block with a word line enabled signal in response to the first word line control signal and the output of the predecoding unit; a third row decoding controller connected to the first row decoding controller, the predecoding unit, and the row decoding and word line driving block, for providing the row decoding and word line driving block with a block selection signal in response to the first word line control signal and the output of the predecoding unit; and a word line driving controller for receiving the second word line control signal and the output of the predecoding unit, and for providing the row decoding and word line driving block with a word line driving signal in response to the first word line control signal and the output of the predecoding unit.
The first row decoding controller may include a transmission gate for transmitting the row address in response to the mode register set signal, a logic circuit for performing a predetermined logic operation with respect to an output of the transmission gate and the active signal to generate the first word line control signal, a transistor connected between the transmission gate and the logic circuit and gated by the precharge signal, for transferring an output of the transmission gate to the logic circuit in response to the precharge signal, and a delay circuit for delaying the first word line control signal for a predetermined time to generate the second word line control signal.
The first row decoding controller, as another embodiment, may include a transistor chain having a plurality of transistors, for lowering a high voltage input by a level depending on the number of the plurality of transistors, a first logic circuit for performing a predetermined first logic operation with respect to an output of the transistor chain and the precharge signal, a transistor gated by a high voltage control signal, for controlling transmission of the output of the transistor chain to the first logic circuit in response to the high voltage control signal, a second logic circuit for performing a predetermined second logic operation with respect to an output of the first logic circuit and the active signal to generate the first word line control signal, and a delay circuit for delaying the first word line control signal for a predetermined time to generate the second word line control signal.
The third row decoding controller may include an inverter chain having a plurality of inverters, for inverting and delaying the first word line control signal, and a logic circuit for operating a predetermined logic operation on the first word line control signal, the output of the inverter chain, and the output of the predecoding unit to generate the block selection signal.
The word line driving controller may include a logic circuit for performing a predetermined logic operation with respect to the second word line control signal and the output of the predecoding unit, an inverter for inverting an output of the logic circuit, and a differential amplifier receiving a supply voltage, for amplifying a voltage difference between the output of the logic circuit and an output of the inverter to generate the word line driving signal.
The row decoding and word line driving block may include a plurality of row decoder and word line drivers, each row decoder and word line driver receiving the output of the predecoding unit, the word line enable signal, the block selection signal, the word line driving signal, and the second word line control signal, for selecting a portion of the plurality of word lines to activate or disable the selected word lines. The row decoder and word line driver includes a row decoder for receiving the output of the predecoding unit, the word line enable signal, the block selection signal, and the second word line control signal, for outputting a ground voltage when the output of the predecoding unit and the block selection are enabled, and for outputting a supply voltage when the word line enable signal is enabled and one of the output of the predecoding unit and the block selection signal is disabled; and a plurality of word line drivers, each word line driver connected to a word line for activating or disabling the word line in respons
Joo Jae-hoon
Kang Sang-seok
F. Chau & Associates LLP
Lam David
Nelms David
Samsung Electronics Co,. Ltd.
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