Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-08-17
2001-04-24
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06223327
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a cell hierarchy verification method and apparatus for an LSI layout and, more particularly, to a cell hierarchy verification method and apparatus for verifying and correcting the hierarchical layout of cell figures forming a gate array LSI layout.
2. Description of the Prior Art
Technical terms used in the description of the present invention will be first explained.
“LSI layout” is a cluster of one or more cells which are hierarchically described.
Figures in the cells of the LSI layout are classified into “diffusion figures” and “polysilicon figures” forming transistors and “wiring figures” connecting the transistors. These figures can be discriminated from each other by integral numbers called layer numbers.
“Cell” represents a processing unit consisting of one or a plurality of necessary figures. Each unit cell has “origin” independent of other cells, and “name” for discriminating the cell from other cells. The discrimination name added to each cell is particularly called “cell name”.
“Cell references figure” means that enough information to represent attributes in a cell such as a figure shape, layout position, and layer number is stored in a predetermined format using the cell origin as a reference.
“Hierarchically described” means that the references of cells are sequentially described using one reference cell as a top. A reference cell serving as a top is particularly called “top cell”. A referencing cell is called “parent cell”, and a referenced cell is called “child cell”. A last-stage cell, which can be reached by sequentially traversing child cells from a specific cell, e.g, a first-stage cell (parent cell), is called “descendant cell of first-stage cell”.
Each layout figure pattern (to be simply referred to as a figure hereinafter) forming a transistor will be described.
FIG. 7
is a perspective view schematically showing a conventional LSI layout in which figures forming a transistor in the manufacturing process are vertically separated. In
FIG. 7
, reference numeral
101
denotes a polysilicon figure; and
102
, a diffusion figure. The polysilicon and diffusion
FIGS. 101 and 102
are laid out so as to divide the diffusion
FIG. 102
into two, right and left regions by the polysilicon FIG.
101
.
FIG. 8A
is a perspective explanatory view three-dimensionally schematically showing the structure of a transistor manufactured based on an LSI layout using the figure layout in FIG.
7
.
FIG. 8B
shows symbols set in advance in order to represent the circuit arrangement. In
FIG. 8A
, the transistor is roughly comprised of a polysilicon wiring layer
111
, a gate
112
, and a pair of diffusion regions
113
and
114
.
The polysilicon wiring layer
111
is formed in correspondence with the polysilicon
FIG. 101
, and the gate
112
is formed in correspondence with the portion where the polysilicon and diffusion
FIGS. 101 and 102
overlap each other. The diffusion regions
113
and
114
are formed in the remaining portions in the diffusion
FIG. 102
that are divided by the overlapping portion with the polysilicon FIG.
101
.
As is well known, the gate
112
, and a portion
115
between the diffusion regions
113
and
114
are subjected to predetermined processing in order to electrically connect the diffusion regions
113
and
114
upon current supply to the polysilicon wiring layer
111
.
That is, these portions
111
to
114
construct one objective transistor.
The schematic arrangement of a cell hierarchy verification apparatus for a conventional LSI layout will be described with reference to
FIGS. 1
to
13
.
FIG. 1
is a block diagram showing the schematic arrangement of a conventional cell hierarchy verification apparatus. In
FIG. 1
, the conventional apparatus comprises an input data section
1
a
having each input data registered in advance in a memory unit such as a hard disk, an input device
2
such as a keyboard or a mouse for instructing apparatus operation, a data processor
3
a
which operates under program control, a memory section
4
a
such as a memory on a computer, an output data section
5
a
for outputting verification data to a memory unit such as a hard disk, and a verification section
6
a
for verifying LSI layouts using verification data and appropriately outputting the verification results.
The input data section
1
a
includes each individual data such as a top cell name
11
, a function block cell name
12
, and LSI layout data
13
. The data processor
3
a
comprises an input unit
31
for reading necessary data from the input data section
1
a
in correspondence with an operation instruction from the input device
2
, a mapping unit
35
for mapping data for each function block cell, and an output unit
34
for outputting a mapped LSI layout.
The memory section
4
a
comprises a general-purpose memory unit
41
for temporarily storing each data read by the input unit
31
, and a cell memory unit
46
used for cell mapping.
The output data section
5
a
includes LSI layout verification data
53
output upon mapping. The verification section
6
a
comprises an appropriate verification means
62
for verifying hierarchy on the basis of the LSI layout verification data
53
, and outputs corrected verification result data and the like.
The operations of the respective building sections in the conventional apparatus will be described.
Upon reception of an instruction from the input device
2
, the input unit
31
of the data processor
3
a
sequentially loads corresponding data from the input data section
1
a
, and temporarily stores them in the general-purpose memory unit
41
of the memory section
4
a
. The mapping unit
35
checks whether a cell to be processed is present for all cells each having a top cell name or a function block cell name stored in the general-purpose memory unit
41
, and maps cells to be processed one by one in accordance with an operation flow shown in
FIG. 2
(step D
1
). Mapping in step D
1
for the cells to be processed is performed in accordance with an operation flow shown in FIG.
3
.
Referring to
FIG. 3
, in step E
1
, cell data are loaded from the general-purpose memory unit
41
and temporarily stored in the cell memory unit
46
. In step E
2
, as shown in
FIG. 4
, the cell data in the cell memory unit
46
are sequentially read out from the first one. Processing of “if the readout data is figure data, sending it to the output unit
34
, erasing it from the cell memory unit
46
, and reading out the next data” is repeatedly performed until all the stored data are processed.
If the readout data is cell reference information in step E
2
, whether the cell name is a function block cell name stored in the general-purpose memory unit
41
is checked in step E
3
. If NO in step E
3
, corresponding cell data is loaded via the input unit
31
. In step E
4
, the coordinate values of the data are transformed into coordinates on the parent cell, and the resultant data is additionally stored at the final address in the cell memory unit
46
. If YES in step E
3
, the reference information is directly sent to the output unit
34
without retrieving the cell contents.
The output unit
34
receives the respective LSI layout data from top cell data in units of function block cell data. The output unit
34
outputs the data to the output data section
5
a
. The output data section
5
a
sequentially stores the mapped data as LSI layout verification data
53
in a memory unit such as a hard disk. The LSI layout verification data
53
are sent to the verification section
6
a
and appropriately verified by the verification means
62
. As a result, data substantially corrected by the verification results are output.
The operation of the conventional apparatus will be explained using detailed input data.
FIG. 5
is an explanatory view showing an example of the cell hierarchical structure of input data in the conventional apparatus. In this example, a top cell name corresponds to bold-line cell A, and function block cell names corre
Do Thuan
NEC Corporation
Smith Matthew
Sughrue Mion Zinn Macpeak & Seas, PLLC
LandOfFree
Cell hierarchy verification method and apparatus for LSI layout does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cell hierarchy verification method and apparatus for LSI layout, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cell hierarchy verification method and apparatus for LSI layout will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2483342