Semiconductor package substrate and semiconductor package

Details Semiconductor package substrate and semiconductor package Semiconductor package substrate and semiconductor package

1999-10-05

2001-01-30

Picard, Leo P. (Department: 2835)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S702000, C361S707000, C361S709000, C257S706000, C257S708000, C257S713000, C174S016300, C165S080300

Reexamination Certificate

active

06181560

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor package substrate and a semiconductor package, and more particularly, to a fabrication method for a column lead package (CLP).
2. Background of the Related Art
FIG. 1
shows a cross-sectional view of a Quad Flat Package, in which a semiconductor chip
3
is mounted on a paddle
2
of a lead frame
1
. The chip
3
is electrically connected to inner leads
1
a
of the lead frame
1
by bonding wires
4
, and the entire whole body
5
except for outer leads
1
b
is encapsulated by an epoxy molding compound.
The Quad Flat Package is disadvantageous since precise alignment of the outer leads
1
b
onto the bonding pads of a printed circuit board (PCB) is difficult. Further, the outer leads
16
may be damaged or deformed due to external impacts during the lead-forming process in which the outer leads
16
are bent into prescribed shapes. The repairing of the chip package defects when mounted on a PCB has been troublesome, and simplification of the fabrication process has been difficult.
SUMMARY OF THE INVENTION
In one embodiment of the present invention, a semiconductor package includes: a plate within which a plurality of leads and a heat sink are embedded; a semiconductor chip attached to the heat sink of the plate; a plurality of metal wires for electrically connecting a plurality of the leads of the plate and the semiconductor chip; and an epoxy molding compound for encapsulating a predetermined portion of the plate.
In alternate embodiments, a recess may be formed in an upper surface plate, and the chip may be mounted in the recess. In this embodiment, a cover member may be attached to upper portions of the plate to encapsulate the chip. The cover may have embedded metallic leads that are in registration with the metallic leads of the plate.
In other embodiments of the invention, a second substrate having a hole at its central portion is stacked on a first substrate to form a combined substrate having a recess, instead of forming a cavity by grinding the central portion of a single semiconductor package substrate.
In each of the embodiments, the leads may be embedded in the substrate such that portions of the leads are exposed along side edges to the substrate. Bond pads of the semiconductor chip may be connected to the leads with metal wires. An insulating material can then be used to package the chip, the metal wires and portions of the leads and the substrate.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.


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