Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-07-02
2001-05-08
Teska, Kevin J. (Department: 2123)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S014000
Reexamination Certificate
active
06230301
ABSTRACT:
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyrights whatsoever.
FIELD OF THE INVENTION
The present invention relates to integrated circuits and in particular to the design, testing, and verification of integrated circuits.
BACKGROUND
Today's integrated circuits (ICs) may contain many circuit elements. Computer-aided design (CAD) and computer-aided engineering (CAE) tools are essential in producing these complicated integrated circuits. Circuit design can be represented by a schematic. Schematics consist of symbols instances connected by nets which demonstrate the functional design of the circuit. Symbol instances are pictorial icons that represent a complete functional block. Symbol instances can be primitive elements, such as transistors and resistors. Symbol instances can also be abstractions of combinations of primitive elements, such as NAND gates and NOR gates. Symbol instances can also be higher level groupings of these various elements.
To produce the complicated schematics of an integrated circuit, CAD software can be used. CAD software allows symbols to be saved in software libraries for use by all circuit designers within the entire IC. Portions of the IC can be easily replicated, deleted, and changed with the CAD software, forming a plurality of sub-circuits.
Another representation of a circuit design is the netlist. A netlist is a text file describing a circuit. The netlist lists all of the symbol instances and their connecting nets within a schematic. CAE software can be used to translate a schematic into a netlist. In a flat netlist, all of the higher levels of symbol instances are replaced by their primitive components. Thus, a schematic having multiple instances of NAND gates would result in a netlist having a collection of transistors.
A netlist is used as input to another CAE tool, the simulator. Simulators use netlists and input stimulus files to imitate the function of the circuit design without having to incorporate the design in hardware. Simulating a circuit by providing netlists and stimulus data is an efficient and cost worthy method of testing a circuit design to determine how the circuit performs prior to fabrication of the circuit as an integrated circuit structure. Circuit performance is determined by a function commonly referred to a probing, whereby currents and voltages are monitored at various points in the circuit design.
Processes have been proposed in the prior art for measuring current and/or voltages internally of sub-circuits of the circuit design. For example, META software available from Cadence Design Systems, Inc., San Jose, Calif., provides a way to measure current by adding a device for each node and then using arithmetic to add up all of the currents. Also, a simulator program, commercially available from ADM, provides a method for measuring current through a sub-circuit in a hierarchical netlist. However, neither one of these arrangements allows for the measurement of current in sub-circuits of a schematic through the application of a supply to the sub-circuits on a global basis for directly measuring current in sub-circuits during testing and verification of the circuit being designed.
SUMMARY OF THE INVENTION
The present invention provides a method and system for allowing the measurement of current in a sub-circuit of a schematic during simulation testing. The current measurement function is provided through the manipulation of a netlist of the schematic, as the netlist is being created, by interpreting instance properties to identify nets through which current flow is to be measured. “Artificial” nets are created and substituted for the nets specified by the instance properties, allowing the connection of a power source to specified nets of the instance.
In accordance with the invention, for each instance that includes a net, or combination of nets, through which current flow is to be measured, a property is assigned to the instance on the schematic, the property identifying the net and the power supply to be connected to the net. A flat netlister formatter provided by the invention is interfaced with a conventional flat netlisting engine, whereby, as the flat netlisting engine creates a flat netlist from the schematic, procedures of the flat netlister formatter interpret each property, replace each net identified by the property with an artificial net, and declare the power supply to be connected between the artificial net and the net originally called out, to allow current flow through the net to be measured during a subsequent simulation.
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Jones Hugh
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
Teska Kevin J.
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