Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-11-29
2001-04-24
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C156S345420, C216S067000, C216S079000, C438S723000, C438S743000
Reexamination Certificate
active
06221784
ABSTRACT:
BACKGROUND OF THE DISCLOSURE
1. Field of Invention
The present invention relates generally to a method and apparatus for dry etching semiconductor wafers. More specifically, the invention relates to a method and concomitant apparatus for anisotropically etching a dielectric layer followed by in situ isotropic etching of a polysilicon layer.
2. Background of Invention
Trenches formed in semiconductor substrates have many uses in producing integrated circuits including isolation, capacitor formation, transistor formation, and so forth. One important use of trenches is in the formation of a trench capacitor as a storage node for a dynamic random access memory (DRAM) device. Trench capacitors are desirable because they occupy a relatively small area, while having large electrode surface area due to the depth of the trench used to form the capacitor.
FIGS. 1A through 1G
collectively depict a portion of a conventional process of manufacturing the DRAM structure. In a first process chamber, a trench
12
is etched into a substrate
14
(FIG.
1
A). The trench
12
is then lined with a first oxide
16
to condition the substrate
14
against dopant migration (FIG.
1
B). The first oxide
16
is removed and a dielectric layer
18
is deposited (FIG.
1
C). The trench
12
is filled and partially etched back with a first layer of polysilicon
20
(FIG.
1
D). A second oxide
22
is deposited covering the first polysilicon layer
20
(FIG.
1
E). The second oxide
22
is anisotropically etched in a second chamber to expose the underlying first layer of polysilicon
20
(FIG.
1
F). A second layer of polysilicon
24
is deposited above the first layer of polysilicon
20
to fill the trench
12
(FIG.
1
G).
Although the foregoing process yields a structure that is effectively used in a DRAM device, the number of process steps, and the number of chambers (both etch and deposition) required to produce the desired structure in the film stack is large. With such a large number of steps, and associated chambers required to execute those steps, the risk of device damage and contamination is correspondingly large as well. Additionally, the large number of steps places a burden on system throughput. For example, in order to anisotropically etch the second oxide to expose the underlying polysilicon, a parallel plate plasma reactor with capacitive coupling is generally used. Since prior art reactors are typically not capable of the selectivity needed to etch the underlying polysilicon without damaging nitride and oxide layers exposed in the film stack, a separate tool is typically used for the polysilicon etching step that follows in some specific process sequences. Etching the underlying polysilicon is performed in an etch reactor with isotropic etch capability. The need for switching chambers to etch the underlying polysilicon after the oxide etch increases the risk of damage to the film stack by exposing the wafer to additional environments and excessive handling.
Therefore, there is a need in the art for a method that clears a high aspect ratio trench, lined with a dielectric, having an anisotropic dielectric etch and an isotropic polysilicon etch sequentially performed in the same process chamber.
SUMMARY OF INVENTION
The disadvantages associated with the prior art are overcome by the present invention which facilitates in situ etching of a substrate comprising both a polysilicon layer and an overlying dielectric layer. The inventive apparatus and concomitant method comprises an anisotropic etch of the dielectric layer using a first fluorinated gas (for example, CF
4
, NF
3
, SF
6
, and other gases comprising fluorine) as an etch gas to expose at least a portion of the underlying polysilicon layer. Following the anisotropic etch and without removing the substrate from the etch chamber, i.e., in situ, performing an isotropic etch on the exposed portions of the underlying polysilicon layer using a second fluorinated gas (for example, CF
4
, NF
3
, SF
6
, and other gases comprising fluorine).
REFERENCES:
patent: 4310380 (1982-01-01), Flamm et al.
patent: 4484978 (1984-11-01), Keyer
patent: 4666555 (1987-05-01), Tsang
patent: 4726879 (1988-02-01), Bondur et al.
patent: 4741799 (1988-05-01), Chen et al.
patent: 5316616 (1994-05-01), Nakamura et al.
patent: 5358601 (1994-10-01), Cathey
patent: 5433823 (1995-07-01), Cain
patent: 5658472 (1997-08-01), Bartha et al.
patent: 5759921 (1998-06-01), Rostoker
U.S. application No. 09/206,201, Chinn et al., filed Dec. 3, 1998.
Schmidt Michael
Schmidt Ursula
Schoenleber Walter
Applied Materials Inc.
Powell William
Thomason Moser & Patterson
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