Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1997-12-18
2001-05-08
Pham, Chi (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S156000
Reexamination Certificate
active
06229864
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to detection circuits which determine whether two input signals have the same frequency and phase. More particularly, the invention relates to a lock condition detector for use with a phase locked loop (PLL) circuit, and to the combination of the two circuits. The invention also relates to a method of detecting a lock condition between two signals.
2. Description of the Prior Art
PLL circuits are used in a variety of applications including microprocessors, digital video systems, and mobile communication devices, such as cell phones. A PLL circuit is used where a clock signal needs to be generated and synchronized to another source, such as an external reference signal. In its most basic form, as illustrated in
FIG. 1
, a PLL circuit includes a voltage controlled oscillator “VCO”
10
, which is an oscillator that can run over a range of frequencies dependant on a control voltage applied to a control terminal of the VCO. The VCO is driven by a phase error between the output of the VCO and the reference signal, measured by a loop phase comparator
20
. This error is used to change the control voltage in such a way that the error between the reference signal and the output of the VCO is reduced, with the goal of maintaining the output of the VCO the same as the reference signal with respect to phase and frequency. Typically, the PLL includes a filter
30
in the control voltage path to provide stability to the control loop. Additionally, by inserting a loop divider
40
between the phase comparator and the VCO, the output of the VCO can be made to be a multiple of the reference signal. The above illustrates the most basic form of a PLL. Examples of some advanced designs of PLL circuits are shown, for example, in U.S. Pat. Nos. 5,349,613; 5,475,718; 5,349,613 and EP 0 433 120 A1.
Despite advances in control mechanisms, it is still possible in many applications for the output signal of the VCO to become out of lock with respect to the reference signal. Out of lock means that the output signal of the VCO differs from the reference signal with respect to phase and/or frequency by a predetermined factor relevant to the application that the PLL is being used for. This may occur, for example, because a component becomes damaged or the desired output frequency is not achievable by the VCO, for example due to a change in the ambient temperature of the circuit or supply voltage. In certain applications, it is desirable that the device, in which the PLL is used, either perform a certain function or not perform a certain function. For example, in a cell phone, transmitting at a non-desired frequency will interfere with other communications and should be avoided. An out of lock condition signal could then be used to avoid transmission.
Accordingly, it is an object of the invention to provide a lock detection circuit which indicates when two signals are out of lock.
It is another object of the invention to provide such a circuit which generates a signal when the out of lock condition is detected to control the operation of device containing the PLL.
SUMMARY OF THE INVENTION
Generally speaking, according to the invention, a lock condition detector includes a phase detector which receives first and second signals and outputs a phase condition signal indicative of the first and second signals being within or outside of a prescribed phase difference. A frequency detector outputs a frequency condition signal indicative of the first and second signals being within or outside of a prescribed frequency difference. An analyzer receives the phase condition signal and the frequency condition signal and generates an out of lock condition signal indicative of the first and second signals being out of lock whenever the phase condition signal indicates that the first and second signals are outside of the phase condition and whenever the frequency condition signal indicates that the first and second signals are outside of the prescribed frequency condition.
The invention is based on the recognition that to determine whether two signals are in lock, it is not sufficient to only detect whether the two signals are in phase. The two signals could be seen as being in phase when the two signals are at frequencies which are multiples of each other. The combination of a frequency detector with a phase detector thus ensures that an out of lock condition signal is generated whenever the two signals are outside of selected frequency relationship, despite the phase detector indicating an in-phase relationship. Additionally, if only a phase detector were used, the output would be a high frequency signal equal to the frequency error between the two signals. For many practical devices, such as with a PLL in a cell phone, such a high frequency signal could not be reliably detected by a microprocessor in the device. The frequency detector thus ensures that a stable, constant out of lock signal is generated whenever the frequency error is greater than a selected value.
According to one aspect of the invention, the phase detector is a D type-flip flop clocked by the reference signal, which outputs the logic value of the oscillator signal.
According to another aspect of the invention, the frequency detector includes first and second dividers dividing each of the first and second signals by a selected divisor. Each divider outputs an end of count signal, which are fed to a second D-type flip flop. The second D-type flip flop then outputs a logic signal indicative of whether the first and second signals are within or outside of frequency difference equal to the quotient of the reference signal and the divisor.
According to another aspect of the invention, the analyzer implements a combinatorial logic function on the phase condition signal and the frequency condition signal to generate the lock condition signal. In the disclosed implementation, the logic function is simply the AND function.
Another aspect of the invention concerns the combination of a PLL with a lock condition detector. The invention also concerns a method of determining whether two signals are within a specified lock condition.
These and other object, features and advantages of the invention will become apparent with reference to the following detailed description and the drawings.
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Corrielus Jean B
Pham Chi
Philips Electronics North America Corporation
Wieghaus Brian J.
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