Semiconductor device manufacturing: process – Making field effect device having pair of active regions...
Reexamination Certificate
2000-03-09
2001-08-28
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
C438S201000
Reexamination Certificate
active
06281050
ABSTRACT:
RELATED APPLICATION
This application claims benefit of priority under 35 U.S.C. §119 to Japanese Patent Applications No. H11-68017, filed on Mar. 15, 1999, and No. H11-244018, filed on Aug. 30, 1999, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a manufacturing method of a semiconductor device and a nonvolatile semiconductor storage device, and more particularly, to a manufacturing method of those devices which use STI (shallow trench isolation) for isolation of elements.
2. Description of the Related Art
Recently, isolation of elements by SA-STI (self-aligned shallow trench isolation) has come be employed in place of conventional LOCOS methods as a method for isolation of elements required for miniaturization of semiconductor devices. One of problems with isolation of elements using STI is the nonvolatile semiconductor storage device which needs to generate a high potential for effecting erase/program(write) operations using a tunnel oxide film.
The nonvolatile semiconductor storage device needs, in addition to a memory cell transistor requiring a tunnel oxide film, a transistor with a thick gate oxide film for generating a high potential (high voltage-withstanding transistor) and a thin gate oxide film for effecting low-power, low-voltage operations (low voltage-withstanding transistor). That is, it needs three kinds of transistors: memory cell transistor, high voltage-withstanding transistor, low voltage-withstanding transistor. For making these three kinds of transistors, thickness of the oxide film of the low voltage-withstanding transistor is the thinnest, thickness of the tunnel oxide film of the memory cell transistor is the next, and thickness of the oxide film of the high voltage-withstanding transistor is the thickest. On the other hand, thickness of the tunnel oxide film of the memory cell transistor may be the thinnest, thickness of the oxide film of the low voltage-withstanding transistor may be the next, and thickness of the oxide film of the high voltage-withstanding transistor may be the thickest.
In these nonvolatile semiconductor storage devices requiring differentiation in thickness among a plurality of gate oxide films, deterioration of the transistor performance by depression of STI arises as a problem.
FIG. 12
is a cross-sectional view of a nonvolatile semiconductor storage device under its manufacturing process, taken to explain depression of STI, and
FIG. 13
is a plane view taken from the top of FIG.
12
. That is,
FIG. 12
is a cross-sectional view taken along the A—A line of FIG.
13
. These
FIGS. 12 and 13
illustrate a MOS transistor.
As shown in
FIGS. 12 and 13
, depressions
106
appear in STI regions
104
. The depressions
106
in the STI regions
104
are caused by a film decrease in the STI regions
104
upon oxide film etching conducted for forming an oxide film different in thickness from the gate oxide film
108
in the active regions
102
of the semiconductor substrate
100
. When the film decrease occurs, surfaces of the STI regions
104
in the perimeter portions sink into the semiconductor substrate
100
from the surface level of the active region
102
.
As shown in
FIG. 13
, once the depressions
106
are produced at perimeter portions of the STI regions
104
to surround the active regions
102
, as shown in
FIG. 12
, gate electrodes
110
also sink into the depressions
106
. When the gate electrodes
110
sink, the depressed perimeter regions are affected by side surface portions of the active regions
102
, and invite the anomaly that kinks occur in sub-threshold regions of MOS transistors.
FIG. 14
is a diagram which shows relationship between the gate voltage Vg and log Id of the source/drain current Id of a transistor including kinks.
As shown in
FIG. 14
, when kinks occur, the cut-off property of the MOS transistor deteriorates, and the off leakage current increases. This invites various problems such as instability of the circuit operation, increase of power consumption in the standby mode.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to prevent that depressions are produced in STI perimeter regions in a semiconductor device having STI when a plurality of oxide films different in thickness are formed. Additionally, thereby, the invention intends to prevent an increase of the off leakage current by improving the cut-off property of a MOS transistor. That is, it is the object of the invention to provide a semiconductor device and a nonvolatile semiconductor storage device having a MOS transistor which is stable in circuit operation and reduced in power consumption in the standby mode.
According to the invention, there is provided a manufacturing method of a semiconductor device comprising the steps of:
making on a semiconductor substrate a first pattern mask having an aperture in a trench isolation forming region;
making an isolation aperture in the semiconductor substrate by using the first pattern mask;
narrowing the width of the first pattern mask to form a second pattern mask having a first mask with a first width and a second mask with a second width narrower than the first width;
forming a buried insulating film which buries the isolation aperture and extends onto the pattern mask;
removing the second pattern mask, then making a first aperture with the first width in a portion of the buried insulating film from which the first mask has been removed, and making a second aperture with the second width in a portion of the buried insulating film from which the second mask has been removed;
forming a first insulating film with a first thickness on the bottom surface of the first aperture and the bottom surface of the second aperture;
removing the first insulating film formed on the bottom surface of the second aperture while maintaining the first insulating film formed on the bottom surface of the first aperture; and
forming a second insulating film different in thickness from the first insulating film on the bottom surface of the second aperture.
According to the invention, there is further provided a manufacturing method of a nonvolatile semiconductor storage device including a memory cell transistor forming region for forming a memory cell transistor, and a peripheral transistor forming region for forming a peripheral transistor for the memory cell transistor, comprising the steps of:
making on a semiconductor substrate a first pattern mask having an aperture in a trench isolation forming region;
making an isolation aperture in the semiconductor substrate by using the first pattern mask;
narrowing the width of the first pattern mask to form a second pattern mask having a first mask with a first width in the memory cell transistor forming region and a second mask with a second width narrower than the first width in the peripheral transistor forming region;
forming a buried insulating film which buries the isolation aperture and extends onto the pattern mask;
removing the second pattern mask, then making a first aperture with the first width in a portion of the buried insulating film located in the memory cell transistor forming region, from which the first mask has been removed, and making a second aperture with the second width in a portion of the buried insulating film located in the peripheral transistor forming region, from which the second mask has been removed;
forming a first insulating film with a first thickness on the bottom surface of the first aperture located in the memory cell transistor forming region and the bottom surface of the second aperture located in the peripheral transistor forming region;
removing the first insulating film formed on the bottom surface of the second aperture located in the peripheral transistor forming region while maintaining the first insulating film formed on the bottom surface of the first aperture located in the memory cell transistor forming region;
forming a second insulating film different in thickness from the first insulating film on the b
Kabushiki Kaisha Toshiba
Nelms David
Nhu David
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
LandOfFree
Manufacturing method of a semiconductor device and a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Manufacturing method of a semiconductor device and a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Manufacturing method of a semiconductor device and a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2481346