Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Reexamination Certificate
1999-12-06
2001-05-08
Gossage, Glenn (Department: 2759)
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
C711S217000, C711S167000, C711S105000, C711S104000, C365S230080, C365S233100, C710S035000, C710S061000
Reexamination Certificate
active
06230250
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a dynamic random access memory (DRAM) arranged for operating in a data processing system.
BACKGROUND OF THE INVENTION
In the past, semiconductor dynamic random access memory operated faster than the associated microprocessor. During the late 1970's and early 1980's, the microcomputer market was in the early stages of development. At that time, a microcomputer system included a microprocessor and a dynamic random access memory. In a microcomputer arrangement, the microprocessor ran synchronously in response to a clock signal, but the dynamic random access memory ran asynchronously with respect to the operation of the microprocessor. The microprocessor clock was applied to a controller circuit that was interposed between the microprocessor and the dynamic random access memory. In response to the microprocessor clock signal, the controller derived other control or clock signals which ran the dynamic random access memory operation.
Typical operating speeds of the microprocessor and the dynamic random access memory were different from each other. A microprocessor cycle time was in a range of 400-500 nanoseconds while a dynamic random access memory cycle time was approximately 300 nanoseconds. Thus the dynamic random access memory was able to operate faster than its associated microprocessor. The memory completed all of its tasks with time to spare. As a result, the microprocessor operated at its optimum speed without waiting for the memory to write-in data or read out data.
Subsequently, as the semiconductor art developed, the operating speeds of microprocessors and memory devices have increased. Microprocessor speeds, however, have increased faster than dynamic random access memory speeds. Now microprocessors operate faster than their associated dynamic random access memory. For instance, a microprocessor cycle time is approximately 40 nanoseconds and a dynamic random access memory cycle time is approximately 120 nanoseconds. The microprocessor completes all of its tasks but must wait significant periods of time for the dynamic random access memory.
Having the microprocessor waiting for the memory is a problem that has been attracting the attention of many microcomputer designers. High speed static cache memories have been added to the microcomputer systems to speed up access to data stored in the memory. A significant part of the problem is to speed up access to data in the memory without significantly increasing the cost of the microcomputer system. Cache memory, however, is significantly more expensive than dynamic random access memory.
An existing problem with dynamic random access memory devices is that they require a substantial amount of peripheral circuitry between the microprocessor and the memory for generating several control signals. So many interdependent control signals are generated by long logic chains within the peripheral circuitry that microcomputer systems designers must resolve very complex timing problems. The delay caused by the timing problems and the fact that memories now are accessed slower than the associated microprocessor cause problems of excessive time delays in microcomputer system operations.
In addition to the foregoing problems, the prior art arrangements, such as described in U.S. Pat. No. 5,390,149, include many control leads between the microprocessor and the dynamic random access memory. Those control leads include several chip-to-chip interconnections. Generally, integrated circuit designers desire to reduce the number of off-chip leads from a device. Thus, there is a problem in actually reducing the number of off-chip leads between the microprocessor and the dynamic random access memory.
SUMMARY OF THE INVENTION
These and other problems are solved by a digital processor and a system clock circuit for producing a system clock signal having timing edges for controlling operation of the digital processor. A synchronous random access memory, directly responsive to the edges of the system clock signal and an address select signal, is arranged for accessing addressable storage cells within the synchronous dynamic random access memory to write data into the storage cells or read data out from the storage cells. Row address strobe (RAS) and column address strobe (CAS) control signals are not required because row and column address timing is initiated by the single address select signal. This synchronous random access memory device may be fabricated as a dynamic or as a static storage device.
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Gossage Glenn
Rountree Robert N.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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