Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
1999-08-04
2001-07-03
Wamsley, Patrick (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S083000, C327S534000
Reexamination Certificate
active
06255851
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to input/output (I/O) buffer circuits that are compatible with multiple voltage levels.
BACKGROUND OF THE INVENTION
Conventional circuit components generally operate between approximately 3 and 5 volts. In recent history, circuit components were typically designed to operate at approximately 5 volts. Today, however, low voltage components which operate at approximately 3 volts are becoming more popular in circuit designs because of their low power consumption and high performance. Currently, it is often desirable to have a 3 volt circuit designed with 3 volt components to communicate with a 5 volt circuit designed with 5 volt components. Damage to circuits designed using 3 and 5 volt technologies can result from combining the technologies if appropriate steps are not taken to make them compatible.
In addition to damage resulting from interconnecting circuits designed in 3 and 5 volt technologies, over-voltages (voltages that are greater than the power supply voltage of a circuit) may also cause damage to circuitry. Over-voltages can be introduced to input/output circuitry by circuits which interface with the input/output circuit. For example, ringing may occur on a metal trace of a printed circuit board due to inductive effects which may cause over-voltages at the input/output interface to occur. Over-voltages may potentially damage both 3 and 5 volt circuits.
In order to provide a guide for developers in designing telecommunications equipment, specifications have been created to offer such developers connection standards for safely connecting circuits to one another. These specifications set forth requirements and conditions for connections. For example, requirements for active clamping (circuitry to prevent the voltage level from exceeding a certain value) and system power supply values may be set forth in a specification.
Standard specifications, such as the PCI bus specification (PCI Local Bus Specification, Revision 2.1) which is an industry standard, require that the output of an I/O buffer be actively clamped to guard against system over-voltages. Prior art circuits have been successful in protecting against system over-voltages by actively clamping the I/O port to the input/output bus power supply. A basic prior art I/O buffer circuit pull-up transistor with active clamping is shown in FIG.
1
. The buffer circuit pull-up transistor
10
comprises a p-channel transistor
12
. The p-channel transistor
12
has a gate
12
A, source
12
B, drain
12
C, and back-gate
12
D. Transistor
12
is connected as follows: gate
12
A is connected to a signal which controls the transistor
12
; source
12
B is connected to a buffer circuit power supply, V
DD
; drain
12
C is connected to an I/O port; and back-gate
12
D is connected to a destination.
Inherent to fabricated p-channel transistors age p-n junctions which create parasitic diodes
14
and
16
between the drain and the substrate, and between the source and the substrate, respectively. The parasitic diodes are illustrated in
FIG. 1
at
14
and
16
. One parasitic diode
14
is inherent to the fabricated junction between the source
12
B and the back-gate
12
D, and another parasitic diode
16
is inherent to the fabricated junction between the drain
12
C and the back-gate
12
D.
If V
IO
is at 5 volts (i.e., the bus is in 5 volt signaling mode) and V
DD
is at 3 volts, diode
14
is reversed bias and I/O port
18
can swing between 0 and 5 volts. Since diode
14
is reverse biased, no damaging currents will be allowed to flow through that junction, i.e., between the back-gate
12
D and the source
12
B. If the voltage level at the I/O port
18
swings above 5 volts, parasitic diode
16
clamps I/O port
18
to the back-gate
12
D voltage level of 5 volts. Parasitic diode
16
provides active clamping to the input/output bus power supply, V
IO
.
If V
IO
is at 3 volts (i.e., the bus is in 3 volt signaling mode) and V
DD
is at 3 volts, diode
14
is not biased and I/O port
18
can swing between 0 and 3 volts. Since diode
14
is not forward biased, no damaging currents will be allowed to flow through that junction. If the voltage level at the I/O port
18
swings above 3 volts, parasitic diode
16
clamps I/O port
18
to the back-gate
12
D voltage level of 3 volts. Parasitic diode
16
provides active clamping to the input/output bus power supply, V
IO
.
A recent specification (i.e., PCI Local Bus Specification, Revision 2.2) provides that in addition to actively clamping the I/O port, the PCI power supply will be allowed to be powered down (voltage allowed to go to ground). This presents a problem for basic prior art I/O buffer circuits. Given the circuit shown in
FIG. 1
, if the voltage, V
IO
, at back-gate
12
D is allowed to go to ground and the voltage, V
DD
, at source
12
B is at three volts, parasitic diode
14
will be heavily forward biased. The heavily forward biased parasitic diode
14
would pass sufficient current to destroy transistor
12
. For example, MOS transistors would be damaged if they were subjected to a high current flow. In such a case, there is a potential for degraded reliability and damage to the MOS transistors contained in a 3 volt circuit due to the current created by the 3 volt potential between source
12
B at 3 volts and back-gate
12
D at ground.
Prior art circuits such as the circuit shown in
FIG. 1
have been effective in accommodating multiple voltage levels and handling over-voltages, however, they do not conform to the most recent PCI specification (Release 2.2) which requires that the bus power supply be allowed to go to ground. Existing prior art circuits require that either the power supplies are always active, or they do not provide active clamping of the input port
18
.
SUMMARY OF THE INVENTION
The present invention discloses an improved output portion of an input/output (I/O) buffer circuit that is compatible with multiple voltage levels. The buffer circuit provides active clamping to guard against system over-voltages by connecting the substrate of a pull-up transistor to an input/output bus power supply. It also contains protection circuitry which protects the circuit by isolating the input/output bus power supply from the substrate of the buffer circuit pull-up transistor in the event that the input/output bus power supply is powered down (i.e., goes to zero volts).
The protection circuitry is implemented by using voltage dividers, comparators, and logic gates to control a protection transistor. The logic gates are dependent on the voltage levels of the buffer circuit power supply and the input/output bus power supply. If the input/output bus power supply is allowed to go to ground, the protection transistor is turned off, which causes the buffer circuit pull-up transistor substrate to float rather than go to ground. Since the substrate of the pull-up transistor is floating, potentially damaging currents are prevented from flowing through the pull-up transistor.
REFERENCES:
patent: 5144165 (1992-09-01), Dhong et al.
patent: 5381062 (1995-01-01), Morris
patent: 5424659 (1995-06-01), Stephens et al.
patent: 5448198 (1995-09-01), Toyoshima et al.
patent: 5661414 (1997-08-01), Shigehara et al.
patent: 5854561 (1998-12-01), Arimoto et al.
patent: 5880602 (1999-03-01), Kaminaga et al.
Agere Systems Guardian Corp.
Le Don Phu
Synnestvedt & Lechner LLP
Wamsley Patrick
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