Method for preventing poisoned vias and trenches

Details Method for preventing poisoned vias and trenches Method for preventing poisoned vias and trenches

1998-10-07

2001-05-01

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S594000, C438S723000, C438S734000, C438S740000, C438S743000

Reexamination Certificate

active

06225204

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87112288, filed Jul. 28, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for fabricating multilevel interconnects, and more particularly, to a method for preventing the occurrence of poisoned vias and trenches.
2. Description of Related Art
A dual damascene process is a technique which imbeds interconnects into an insulator. This process includes forming an insulator, planarizing and patterning the insulator to form trenches and via holes, and filling the trenches and via holes with metal to form conducting wires and via plugs. A chemical mechanical polishing process is then performed to planarize the surface of a device. Because a dual damascene process prevents the occurrence of overlay error and process bias of a conventional metallization process, it has been widely applied in semiconductor processes to improve the reliability of devices.
FIGS. 1A through 1D
are schematic, cross-sectional views illustrating the steps taken in a conventional method for fabricating a dual damascene structure.
Referring to
FIG. 1A
, a substrate
100
contains a metal layer
102
. A silicon nitride layer
104
, which is used as an etching stop, and a silicon oxide layer
106
, which is used as a dielectric layer, are formed on a provided substrate
100
in sequence by performing chemical vapor deposition processes. A chemical mechanical polishing process is performed to polish the dielectric layer
106
to a desired thickness, the depth of desired via plugs. Then, a silicon-oxy-nitride or silicon nitride layer
108
used as another etching stop and a silicon oxide layer
110
used as another dielectric layer are formed on the dielectric layer
106
in sequence by chemical vapor deposition processes. A chemical mechanical polishing process is performed to ensure that the thickness of the dielectric layer
110
equals the thickness of the conducting wires of the dual damascene structure to be formed in a follow-up process.
Referring next to
FIG. 1B
, the dielectric layer
110
is patterned to form openings
112
, wherein the positions of the openings
112
correspond to the positions of the metal layer
102
underneath.
Referring to
FIG. 1C
, a portion of the etching stop
108
that is exposed within the openings
112
is removed for transferring pattern onto the etching stop
108
. By using another patterned photoresist layer (not shown in figure) and the patterned etching stop
108
as masks, the dielectric layer
106
and
110
are etched to form via holes
116
and trenches
114
. By using etching stop
108
as a mask, the etching stop
104
is patterned to expose the metal layer
102
. The trenches
114
and via holes
116
compose the openings
118
of a dual damascene structure.
Referring next to
FIG. 1D
, the openings
118
are filled with a conformal barrier/glue layer
122
, composed of titanium/titanium nitride, and a metal layer
124
, composed of aluminum, to form a dual damascene structure
126
. A chemical mechanical polishing process is performed to remove unwanted barrier/glue layer
122
and metal layer
124
from the top of the dielectric layer
110
.
As the integration of a semiconductor device is increased, the resistance-capacitance delay regarding the parasitic capacitance generated by an inter-metal dielectric layer, such as dielectric layers
110
and
106
as shown in
FIG. 1D
, is worsened. Hence, it is common to utilize low-permittivity dielectric to form inter-metal dielectric in a sub-micron semiconductor fabrication process. Conventionally, the low-permittivity dielectric includes organic materials such as spin-on-polymer (SOP), flare, SILK, parylene, and inorganic materials, such as HSQ and FSG. Since most low-permittivity dielectrics tend to absorb moisture, they cause outgassing phenomena during the process of filling conductive material into the openings
118
. The outgassing phenomena within the dielectric layers further lead to the occurrence of poisoned trenches and vias that degrade the yield and the electrical property of a device.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method for preventing the occurrence of poisoned trenches and vias in a dual damascene structure.
In accordance with the foregoing and other objectives of the present invention, the invention provides a method that mainly includes performing an implantation process on the dielectric layer neighboring and within the dual damascene opening before the opening is filled. The material, which includes phosphorus or arsenic, is implanted into the dielectric layer by a implanter with a angle &thgr; to the normal line perpendicular to the top surface of the substrate. The entire wafer rotates horizontally during the implantation process to ensure that material is evenly implanted into the dielectric layer. The implantation process densifies the surface of the dielectric layer, so that the densified surface of the dielectric layer is able to efficiently prevent the occurrence of poisoned trenches and vias caused by the outgassing phenomena.


REFERENCES:
patent: 6013581 (2000-01-01), Wu et al.

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