Configuration logic to eliminate signal contention during...

Details Configuration logic to eliminate signal contention during... Configuration logic to eliminate signal contention during...

1998-02-04

2001-01-30

Santamauro, Jon (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S046000, C365S240000

Reexamination Certificate

active

06181158

ABSTRACT:

FIELD OF THE INVENTION
1. Background of the Invention
The present invention relates to configuration logic, and in particular to configuration logic to eliminate signal contention during reconfiguration.
2. Description of the Related Art Configuration logic is well known in the art of programmable logic devices (PLDs).
FIG. 1
illustrates a simple multiplexer
10
having three input signals I
1
, I
2
, and I
3
. Configuration memory cells
1
,
2
, and
3
provide their stored values to transistors T
1
, T
2
, and T
3
, respectively. Typically, memory cells
1
,
2
, and
3
comprise static random access memory (SRAM) cells which are well known in the art. To avoid signal contention on multiplexer output line
7
, only one transistor is turned on at any one time.
FIG. 2
illustrates another multiplexer
20
having six input signals I
1
-I
6
. Configuration memory cells
1
,
2
,
3
, and
4
provide their stored values to transistors T
1
A/T
1
B, T
2
A/T
2
B, T
3
A/T
3
B, and T
4
A/T
4
B, respectively. To avoid signal contention on multiplexer output line
7
, only three transistors are turned on at any one time. Specifically, only two transistors of transistors TlA/TlB, T
2
A/T
2
B, and T
3
A/T
3
B are conducting at a time, and either transistor T
4
A or transistor T
4
B is conducting.
Before configuration of multiplexers
10
and
20
, one input signal must be designated as the default input signal (i.e. the designated signal provided to output line
7
). This designation ensures that there are no floating gates in inverter
5
and no undefined state for inverter
6
, thereby ensuring the PLD is initially configured to a known state. In a typical PLD, all memory cells are initialized to logic zeros. To designate the default input signal in multiplexer
10
, the signal of memory cell
1
is inverted, thereby ensuring that transistor T
1
is conducting after initialization. Thus, signal I
1
is designated the default input signal. Similarly to designate the default input signal in multiplexer
20
, one signal from memory cell
4
and the signal of memory cell
1
are inverted. Thus, signal I
1
is also designated the default input signal in multiplexer
20
.
If a user desires input signal I
3
(or I
2
) to be the signal provided on output line
7
, transistor T
1
must be turned off before transistor T
3
(or T
2
) is turned on. Thus, memory cell
1
must be programmed no later than memory cells
2
and
3
. However, before another configuration pattern can be implemented, all memory cells must be set to zero (referred to as memory initialization).
In a PLD configuration, the memory cells are typically arranged in groups. During memory initialization, memory cells are set to zero in a systematic manner, typically group by group progressing from right to left (commonly referred to as “housecleaning”). Because the memory cells associated with the default signals (i.g. the memory cells having associated inverters) are positioned to the right of the other memory cells (see FIGS.
1
and
2
), this memory initialization results in signal contention. For example, referring to
FIG. 1
, memory cell
1
if set to zero turns on transistor T
1
which then begins to conduct before memory cell
3
is set to zero. Thus, both transistors T
1
and T
3
are conducting during the same period, thereby creating a signal contention on output
7
.
One solution to this contention problem is to force all input signals to zero when a memory initialization occurs. However, this solution disadvantageously adds logic to the PLD, thereby significantly increasing the silicon area required for the PLD. Moreover, the added logic decreases performance of the PLD itself.
Another solution is to disconnect all lines from all drivers when memory initialization occurs. As is well known in the art, a signal on output line
7
subsequently drives other circuits and devices in the PLD. To avoid signal contention, a pass transistor T
5
(shown for illustration in
FIG. 1
) must be placed on output line
7
, thereby allowing output line
7
to be disconnected (by providing a logic zero signal
11
) during memory initialization. However, this solution also adds logic to the PLD which undesirably increases the silicon required to implement the PLD. Additionally, this added logic significantly deteriorates the performance of the PLD.
Therefore, a need arises for a configuration method and structure which prevents signal contention during memory initialization without adversely affecting either silicon area or PLD performance.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, a structure for providing the clearing and/or programming includes a plurality of synchronous storage elements and a plurality of associated two-input multiplexers. A control signal in a first logic state provided to the multiplexers provides a first signal propagation direction through the storage elements and the control signal in a second logic state provided to the multiplexers provides a second signal propagation direction through the storage elements. In one embodiment, the storage elements are flip-flops, wherein a multiplexer selectively provides (1) a signal from the Q-output terminal of a first flip-flop, or (2) a signal from the Q-output terminal of a second flip-flop or a token signal.
One method for clearing and programming a programmable logic device includes arranging a plurality of memory cells in sets, clearing the sets in a first spatial sequence, and programming the sets in a second spatial sequence, wherein the first spatial sequence is different than the second spatial sequence. In one case, the spatial sequence is a linear progression across the device. A spatial sequence during programming which is the reverse order of the spatial sequence during clearing prevents signal contention. Thus, the present invention provides the flexibility of clearing or programming sets of memory cells in predetermined areas of the device before other areas.
In accordance with another embodiment of the present invention, sets of memory cells could include columns of memory cells, each column having an associated storage element. In this manner, a plurality of columns of memory cells can be cleared or programmed in any predetermined order. Thus, a method for programming a logic device may include programming a plurality of columns of memory cells in a first direction, and then programming another plurality of columns of memory cells in a second direction. A reverse order is preferably used for clearing that logic device. Note that within one plurality of columns, any spatial sequence could be provided.


REFERENCES:
patent: 4758985 (1988-07-01), Carter
patent: 4899307 (1990-02-01), Lenoski
patent: 4961169 (1990-10-01), Matsumura et al.
patent: 4969126 (1990-11-01), Maeno
patent: 4975640 (1990-12-01), Lipp
patent: 5255220 (1993-10-01), Filliman
patent: 5282234 (1994-01-01), Murayama et al.
patent: 5291457 (1994-03-01), Asato et al.
patent: 5363424 (1994-11-01), Fujisawa
patent: 5770951 (1998-06-01), Cheung et al.
patent: 227597 (1990-01-01), None
IBM Technical Disclosure, vol. 28, No. 1, Jun. 1985, pp. 44-46.

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