Electrostatic discharge protection circuit

Details Electrostatic discharge protection circuit Electrostatic discharge protection circuit

2000-03-20

2001-08-28

Mintel, William (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S371000, C257S355000

Reexamination Certificate

active

06281554

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an electrostatic discharge protection circuit, and more particularly to a gate coupled electrostatic discharge protection circuit which is formed with parasitic capacitors generated using a principle of gate couple, to ensure that parasitic bipolar junction transistors can be speedily turned on to protect a related high-voltage device from damages.
2. Description of the Prior Art
In semiconductor industry, electrostatic discharge (ESD) is always a main reason to cause damages on ICs during manufacturing. For example, under an environment with higher relative humidity (RH), there will be several hundred, even several thousand, voltages of electrostatic charges detected when a person walks through a rug. In an environment with lower relative humidity, electrostatic charges will reach more than ten thousand voltages. When the rug or person bringing high-voltage electrostatic charges contacts a chip, the electrostatic charges will be discharged toward the chip, causing irretrievable damages on the chip. To prevent chips from any damages caused by electrostatic charge discharge, various electrostatic discharge protection circuits have been developed. Typically, in the prior art, an on-chip electrostatic discharge protection circuit is designed between an internal circuit and each pad for protecting the internal circuit from damages.
Referring to
FIG. 1
, a structure of a conventional high-voltage electrostatic discharge protection circuit is shown. In the conventional high-voltage electrostatic discharge protection circuit, a high-voltage N-well region
12
and a high-voltage P-well region
14
adjacent to each other are formed in an N-type substrate
10
. A PMOS transistor
16
is formed on the high-voltage N-well region
12
. The PMOS transistor
16
has its gate
18
and source
20
electrically connected to a high voltage V
DD
, together and its drain electrically connected to an input/output pad (I/P PAD)
23
.
The source
20
is constructed by a P
+
-type region
24
, a P-grad region
26
and a P-drift region
28
. The P-grade region
26
is beneath and sounding the P
+
-type region
24
. The P-drift region
28
is adjacent to the P-grade region
26
, partly under the gate
18
. Similarly, the drain
22
is constructed by a P
+
-type region
30
, a P-grade region
32
and a P-drift region
34
. The P-grade region
32
is beneath and surrounding the P
+
-type region
30
. The P-grade region
32
is beneath and surrounding the P
+
-type region
30
. The P-drift region
34
is adjacent to the P-grade region
32
, partly under the gate
18
. Furthermore, on the high-voltage N-type well region
12
, there are an N
+
-base connection region
38
electrically connected to the high voltage V
DD
and a first isolation region
36
, wherein the source
20
and the N
+
-base connection region
38
are adjacent to both sides of the first isolation region
36
.
Similarly, an NMOS transistor
42
is formed on the high-voltage P-well region
14
. The NMOS transistor
42
has its gate
44
and source
46
electrically connected to ground V
SS
, together and its drain
48
electrically connected to the input/output pad
23
. The drain
48
is constructed by an N
+
-type region
50
, an N-grade region
52
and an N-drift region
54
. The N-grade region
52
is beneath and surrounding the N
+
-type region
50
. The N-type drift region
54
is adjacent to the N-grade region
52
, partly under the gate
42
. The source
46
is constructed by an N
+
-type region
56
, an N-grade region
58
and an N-drift region
60
. The N-grade region
58
is beneath and surrounding the N
+
-type region
56
. The drift region
60
is adjacent to the N-grade region
58
, partly under the gate
44
. Moreover, on the high-voltage P-well region
14
, there are an P
+
-base connection region
64
electrically connected to the ground V
SS
, wherein the source
46
and the P
+
-base connection region
64
are adjacent to both sides of a second isolation region
62
. Additionally, there is a third isolation region
40
is formed on the N-type substrate
10
and between the high-voltage N-well region
12
and the high-voltage P-well region
14
. In other words, the drain
22
of the PMOS transistor
16
and the drain
48
of the NMOS transistor
42
are located on both sides of the third isolation region
40
.
Due to the requirement of high-voltage process, the P-well region
14
is formed with high resistance. Consequently, two parasitic bipolar junction transistors
66
,
68
shown in
FIG. 1
have a higher breakdown voltage (BV). Meanwhile, as shown in
FIG. 2
, the gates of the PMOS transistor
16
and the NOMS transistor are electrically connected to V
DD
and V
SS
. As a result, it is uneasy to turn on the parasitic bipolar transistors
66
and
68
to release electrostatic charges in a short time.
SUMMARY OF THE INVENTION
In view of the above, the invention is to provide a high-voltage electrostatic discharge protection circuit, which is formed with parasitic capacitors generated using a principle of gate couple, to ensure that parasitic bipolar junction transistors can be speedily turned on to protect a related high-voltage device from damages.
A high-voltage electrostatic discharge protection circuit according to the invention has the following structure. A first high-voltage N-well region, a first high-voltage P-well region, a second high-voltage N-well region and a second high-voltage P-well region are adjacent to each other. A PMOS transistor is formed on the first high-voltage N-well region and has its source electrically connected to a high voltage and its drain electrically connected to an input/output pad. A first isolation region is formed between the first high-voltage N-well region and the first high-voltage P-well region and electrically connected to the drain of the PMOS transistor. A first N
+
-type region is formed between the first high-voltage P-well region and the second high-voltage N-well region, adjacent to the first isolation region and electrically connected to the input/output pad. A polysilicon gate region is formed on the second high-voltage N-well region, adjacent to the first N
+
-type region and electrically connected to the gate of the PMOS transistor. An NMOS transistor has its drain located between the second high-voltage N-well region and the second high-voltage P-well region and adjacent to the polysilicon gate region and its gate and source located on the second high-voltage P-well region, wherein the drain is electrically connected to the input/output pad, the gate is electrically connected to the polysilicon gate region and the source is electrically connected to a ground voltage.


REFERENCES:
patent: 5689132 (1997-11-01), Ichikawa
patent: 2-234462 (1990-09-01), None

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