Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-06-30
2001-07-03
Bocure, Tesfaldet (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S375000
Reexamination Certificate
active
06256362
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention is related in general to the field of frequency synthesis and clock recovery circuits. More particularly, the invention is related to a frequency acquisition circuit for a phase locked loop.
BACKGROUND OF THE INVENTION
Clock recovery circuits for telecommunications applications, and industrial and automotive control applications require digital and analog phase locked loop circuits to generate clock and timing signals from a reference frequency. For example, clock signals may be generated in this manner for microprocessors that control certain automobile functions, such as instrument panel displays, window controls, anti-lock brakes, engine functions, etc. Phase locked loop circuits used in these applications use a phase detector that is typically exclusive-OR (XOR) gate-based, which possess the desirable characteristic of good noise immunity. Because noise in the typical operating environment may corrupt the reference frequency, the phase locked loop may lock to the wrong frequency at twice or half of the reference frequency, for example, or lose lock entirely. Further, because there is no mechanism to detect the loss of lock or to regain lock onto the correct reference frequency, the resultant clock signal may cause the controlled apparatus or function to malfunction and fail.
One solution to this problem is to detect a loss of lock condition and then requiring the phase locked loop to go through a complete reset cycle. However, this solution causes the system to go off line. Further, it is difficult to implement a loss of lock detector in a high noise environment that does not generate erroneous results.
SUMMARY OF THE INVENTION
Accordingly, there is a need for a method and apparatus that aides in the locking of a phase locked loop to the correct frequency and that aides in recovering from loss of lock conditions.
In accordance with the present invention, a frequency acquisition circuit and method are provided which eliminate or substantially reduce the disadvantages associated with prior circuits and methods.
In one aspect of the invention, a circuit for aiding proper frequency lock in a phase locked loop includes a phase detector adapted for receiving an input signal and an oscillator output signal from the phase locked loop and generating an up and a down pulse width modulated signal indicative of a cycle slip between the input signal and the oscillator output signal. An up cycle slip circuit receives the up pulse width modulated cycle slip signal and generates an up cycle slip signal indicative that the oscillator output signal is lagging behind the input signal. A down cycle slip circuit is adapted for receiving the down pulse width modulated cycle slip signal and generating a down cycle slip signal indicative that the oscillator output signal is ahead of the input signal. A phase correction circuit is provided for generating a steering signal in response to the up and down cycle slip signals.
In another aspect of the invention, a method for aiding proper frequency lock in a phase locked loop includes the steps of detecting a phase difference between an input signal and an oscillator output signal from the phase locked loop and generating an up and a down pulse width modulated signal indicative of a cycle slip between the input signal and the oscillator output signal. An up cycle slip signal is then generated in response to the up pulse width modulated signal indicative that the oscillator output signal is lagging behind the input signal, and a down cycle slip signal is generated in response to the down pulse width modulated signal indicative that the oscillator output signal is ahead of the input signal. A steering signal is then produced in response to the up and down cycle slip signals which is then provided to the phase locked loop to increase or decrease the frequency of the oscillator output signal.
A technical advantage of the present invention is that a mechanism and method are provide to wrap around an existing phase locked loop to allow it to reacquire lock in case of a glitch, prevent false locking to the wrong frequency, and detect unlock conditions.
REFERENCES:
patent: 4808884 (1989-02-01), Hull et al.
patent: 4902920 (1990-02-01), Wolaver
patent: 5111151 (1992-05-01), Ii
patent: 5790613 (1998-08-01), Tateishi
patent: 5910753 (1999-06-01), Bogdan
patent: 6078634 (2000-06-01), Basshart
Bocure Tesfaldet
Brady III W. James
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Frequency acquisition circuit and method for a phase locked... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Frequency acquisition circuit and method for a phase locked..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Frequency acquisition circuit and method for a phase locked... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2476939