Method fabricating a DRAM cell with an area equal to four...

Details Method fabricating a DRAM cell with an area equal to four... Method fabricating a DRAM cell with an area equal to four...

1998-02-12

2001-03-06

Tran, Minh Loan (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S302000, C257S329000

Reexamination Certificate

active

06198121

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process used to fabricate dynamic random access memory, (DRAM), devices, and more specifically to a fabrication process in which the area of the DRAM cell is reduced by stacking the capacitor structure over the access transistor.
2. Description of the Prior Art
In order to satisfy demands for high density DRAM semiconductor chips, micro-miniaturization, or the use of sub-micron features, used for DRAM designs, are employed. The attainment of micro-miniaturazation, or sub-micron features, has been mainly accomplished by advances in specific semiconductor fabrication disciplines, such as photolithography and dry etching. The use of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials, have allowed sub-micron images to be created in photoresist layers. In addition the development of more advanced dry etching tools and etch recipes, have allowed the sub-micron images in overlying photoresist layers to be successfully transferred to underlying materials, used in the creation of advanced semiconductor devices.
However to achieve DRAM densities of 256 megabits, or greater, new designs may be needed. Currently the area needed for a DRAM cell is equal to about eight times the minimum feature used, sometimes referred to as 8F
2
. The creation of DRAM devices, with an area only four times the minimum used feature, 4F
2
, is limited by two basic elements in the DRAM cell, the word line transistor and the storage capacitor. These two elements can not use the same space on the semiconductor chip, if 4F
2
is to be realized. To achieve a DRAM area of 4F
2
these two elements have to be aligned vertically.
This invention will describe a fabrication process for a DRAM cell, in which 4F
2
is achieved by vertically aligning the polysilicon capacitor structure and the gate polysilicon structure, while using an underlying bit line, embedded in the device isolation insulator. Prior art, such as Dhong, et al, describe a method for forming a folded bit line DRAM cell, however that process differs from the present invention in many key areas, such as their use of polysilicon filled trenches, as capacitors.
SUMMARY OF THE INVENTION
It as an object of this invention to create a DRAM cell, consuming an area equal to about four times the minimum design feature.
It is another object of this invention to create a DRAM cell in which the word line and storage capacitor structure, are vertically aligned, occupying the same semiconductor substrate space.
It is still another object of this invention to use an bit line, embedded in an isolation insulator layer.
It is still yet another object of this invention to use a metal silicide spacer, on the sides of the polysilicon gate structure, to reduce gate resistance.
In accordance with the present invention a method for creating a DRAM cell, with a reduced area, by vertically aligning a polysilicon capacitor, and polysilicon gate structure, as well as using embedded bit lines, has been developed. Recessed regions, in a first insulator layer, are partially filled with metal silicide, followed by the deposition of an overlying, second insulator layer, resulting in embedded, metal silicide bit lines. A deposition of a doped, first polysilicon layer, is followed by patterning, using photolithographic and dry etching procedures, creating the polysilicon word line structure. A thin metal silicide spacer is next formed on the sides of the polysilicon word line structure, followed by the deposition of a third insulator layer. Photolithographic and dry etching procedures are again employed to create a narrow device hole in the third insulator layer, in the polysilicon wordline structure, and in the second insulator layer, exposing an embedded bit line region. A gate insulator layer is thermally grown on the sides of the polysilicon wordline structure, exposed in the narrow device hole, followed by the deposition of a first amorphous silicon layer, and a dry etch procedure, used to leave the first amorphous silicon layer, only interfacing the gate insulator layer, on the sides of the polysilicon word line structure. An intrinsic, second polysilicon layer is next deposited, followed by a zero degree ion implantation procedure, resulting in N type doping of the second polysilicon layer in a region directly overlying the embedded bit line region, in the bottom of the narrow device hole, and also creating an N type region in the second polysilicon layer, overlying the third insulator layer, in a region not used for the device hole. A second amorphous silicon layer is then deposited, completely filling the narrow device hole. An anneal is next performed resulting in recrystallization of the amorphous silicon, and the second polysilicon layer, and also creating an N type source and drain region, interfacing the embedded bit line region, at the bottom of the narrow device hole, and an N type source and drain region at the top of the silicon filled, narrow device hole. The recrystallized silicon interfacing the gate insulator layer, in the center of the silicon filled, narrow device hole, used for the channel region, remains undoped. A thick, doped, third polysilicon layer is next deposited and patterned to form the storage node for a capacitor structure, directly overlying the N type source and drain region, in the top of the silicon filled device hole. A capacitor dielectric layer is deposited, followed by the deposition of a fourth polysiliocn layer. Patterning of the fourth polysilicon layer is used to create the cell plate of the capacitor structure, for the DRAM cell.


REFERENCES:
patent: 4974060 (1990-11-01), Ogasawara
patent: 5214603 (1993-05-01), Dhong et al.
patent: 5244837 (1993-09-01), Dennison
patent: 5336629 (1994-08-01), Dhong et al.
patent: 5432739 (1995-07-01), Pein
patent: 5451538 (1995-09-01), Fitch et al.
patent: 5497017 (1996-03-01), Gonzales
patent: 5780888 (1998-07-01), Maeda et al.

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