Method of making an SRAM storage cell with N channel thin...

Details Method of making an SRAM storage cell with N channel thin... Method of making an SRAM storage cell with N channel thin...

1997-11-26

2001-06-26

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S153000, C438S154000, C438S155000, C438S156000, C438S149000

Reexamination Certificate

active

06251713

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuit structures and methods of making such structures and, more particularly, to method of making and structure of an SRAM cell having N channel depletion TFT load devices.
2. Prior Art
CMOS static RAM access memories (SRAM) are used in the semiconductor and computer industries as a result of the combination of speed, low power, and no requirement for refresh. Information can be written into and read out of an SRAM cell faster than with a DRAM cell, because the transistors of the SRAM cell can be switched faster than capacitors can be charged and drained. However, a disadvantage of prior art SRAM cells is that such cells have required a larger footprint to achieve greater speed and stability than DRAM cells.
An SRAM cell can be formed using cross-coupled CMOS inverters having two N channel transistors and two P channel transistors. Typically, the cell is accessed by two N channel control gates for a standard SRAM cell and four control gates for two port memory devices.
There have been many attempts to improve SRAM cells by replacing the P channel transistors with other devices. For example, in same cases, the P channel transistors are replaced with poly silicon resistance back-to-back diodes as resistive load devices. However, the resistance of the back-to-back diode increases significantly at lower voltages and lower temperatures. For example, resistance might be ten times higher at 0° C. as compared to 80° C.
Further, a major single bit failure which has occurred during functional testing of SRAM cells is data retention at low voltage at low temperature. These single bit failures occur when the amount of leakage current at the storage node exceeds the amount of current that can be supplied by the back-to-back diode resistance during low voltage and cold temperature.
One attempt to solve the problem has been to reduce the overall resistance value of the back-to-back diode. However, when the load resistance of a cell is decreased, the amount of standby current is significantly increased, thus increasing power dissipation in the cell.
Another prior art approach has been to employ poly silicon resistance devices as load devices. Although the voltage dependency is lower than that of the back-to-back resistance diode approach, the temperature dependency still prevails with higher resistance values at low to temperature as compared to high temperature resistance.
The P channel MOSFET device provides a low off current and a high on current to sustain leakage of the storage node. However, if the pulldown transistors exhibit high leakage, the Vcc must be electrically disconnected to reduce the standby current. Additionally, for the P channel device, the cell area is much larger than for the other devices described above. Such a cell and the method of making same are taught in U.S. Pat. No. 5,187,114.
Another prior art attempt to solve some of the problems of load devices in SRAM cells has been the use of P channel thin film transistors as the load devices. However, the P channel TFTs are difficult to fabricate with low off current and high on current and further requires the alignment offset of the Drain implant which has a large impact on controlling the on and off current. Further, the P channel TFT has a cell area which is at least 50 percent larger than the back-to-back diode load implementation.
There is a need for an SRAM cell which is relatively immune from voltage variation, which does not require a source/drain offset, which does not require the Vcc line to be disconnected where the pulldown transistors exhibit high leakage current, and which conserves power and energy by controlling current from low Vcc to high Vcc.
SUMMARY OF THE INVENTION
Accordingly, an SRAM cell includes a pair of N channel transistors acting as inverting circuits, a pair of N channel transistors which perform the control function for the cell, and a pair of N channel thin film transistors in depletion mode with gate and source shorted to provide load devices for the N channel inverter transistors of the SRAM cell.
A method for constructing an SRAM cell in accordance with the present invention includes the following steps:
Formation of active and field isolation layer;
Deposition of gate electrode definition and formation of passgate and pulldown transistor;
Deposition of TEOS;
Pattern and etch shared contact
1
(SC
1
);
Deposition of poly silicon layer
2
;
Local interconnect and gate electrode for the N channel TFT;
Implanting phosphorous to desired sheet resistance (rho);
Annealing for predetermined time at predetermined temperature;
Patterning and etching poly silicon layer
2
;
Deposition of TEOS at a predetermined thickness to form gate dielectric for the N channel TFT;
Annealing at a predetermined temperature for a predetermined time;
Pattern and etch layer shared contact
2
(SC
2
);
Deposition of poly silicon layer
3
;
Patterning and etching poly silicon layer
3
;
Blanketing N channel TFT implant;
Patterning TFT;
Implanting N+ TFT source/drain;
Deposition of dielectric; and
Contact and metal interconnection.
It is an advantage of the present invention that an SRAM cell in accordance with the present invention has virtually no dependency on supply voltage, does not require supply voltage to be electrically disconnected where the pulldown transistors have high leakage current, and where the load devices act as constant current sources within the SRAM cell.


REFERENCES:
patent: 5187114 (1993-02-01), Chan et al.
patent: 5364810 (1994-11-01), Kosa et al.
patent: 5460995 (1995-10-01), Klyono et al.
patent: 5471070 (1995-11-01), Shimada et al.
patent: 5514617 (1996-05-01), Liu
patent: 5599729 (1997-02-01), Park
patent: 5731232 (1998-03-01), Wuu et al.
McKenny, Vernon, “Depletion-Mode Devices Hike Speed of MOS Random Access Memory”,Electronics, Feb. 15, 1971 pp. 80-85.
Capece, Raymond P., “The Race Heats Up In Fast Static RAMs”,Electronics, Apr. 26, 1979, pp. 125-135.

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