Data processing: structural design – modeling – simulation – and em – Emulation – In-circuit emulator
Reexamination Certificate
1997-02-19
2001-08-28
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Emulation
In-circuit emulator
C703S027000, C714S726000
Reexamination Certificate
active
06282506
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of designing a semiconductor integrated circuit in which fault detection can be efficiently effected through scan-in and scan-out.
For a scan test for detecting a fault in a semiconductor integrated circuit, the semiconductor integrated circuit is required to be designed so that scan registers, that is, memory elements having a scan test function, are connected with one another to form a scan chain, and the scan chain functions as a shift register in a scan test mode.
In connecting two scan registers for forming a scan chain through the connection of the scan registers, when the scan register at the front stage has two output terminals for positive logic and negative logic, the scan registers are conventionally connected, for example, as follows: The positive logic output terminal alone of the scan register at the front stage is always connected with the scan data input terminal of the scan register at the rear stage; or alternatively, the negative logic output terminal alone of the scan register at the front stage is always connected with the scan data input terminal of the scan register at the rear stage.
Furthermore, as another conventional connection method, when one of the positive and negative logic output terminals of the scan register at the front stage is unconnected, the unconnected output terminal is used for the connection with the scan data input terminal of the scan register at the rear stage. When the two output terminals are both connected with other elements, the positive logic output terminal or the negative logic output terminal is always connected with the scan data input terminal of the scan register at the rear stage.
Now, a conventional method of designing a semiconductor integrated circuit will be described with reference to the accompanying drawings.
FIG. 20
is a circuit diagram of a scan register. In
FIG. 20
, a reference numeral
10
denotes a scan register for fault detection by the scanning method, a reference numeral
11
denotes a data input terminal for receiving a data in a normal operation mode, a reference numeral
12
denotes a scan data input terminal for receiving a scan data in a scan operation mode, a reference numeral
13
denotes a clock input terminal for synchronizing the scan register
10
, a reference numeral
14
denotes an input switch terminal for switching between the normal operation mode and the scan operation mode, a reference numeral
15
denotes a positive logic output terminal for outputting a data having the same value as a data received at the data input terminal
11
or the scan data input terminal
12
, and a reference numeral
16
denotes a negative logic output terminal for outputting a data having a value obtained by inverting a data received at the data input terminal
11
or the scan data input terminal
12
. When “0” or “1” is input through the input terminal
14
, the scan register
10
outputs the data received at the data input terminal
11
and the scan data input terminal
12
through the positive logic output terminal
15
synchronously with a clock signal, and simultaneously outputs, through the negative logic output terminal
16
, an inverted signal of the signal output through the positive logic output terminal
15
.
In the scan register
10
shown in each drawing herein referred to, the scan data input terminal
12
is indicated as SI, the positive logic output terminal
15
is indicated as Q, and the negative logic output terminal
16
is indicated as NQ for convenience, and the scan data input terminal SI, the positive logic output terminal Q and the negative logic output terminal NQ alone are shown in the drawing.
FIG. 25
is a flow chart for showing interconnecting procedures in the conventional method of designing a semiconductor integrated circuit. In the flow chart of
FIG. 25
, in step SZ
1
, connecting order of scan registers is specified; in step SZ
2
, a pair of scan registers adjacent to each other in the scan chain is selected; in step SZ
3
, it is discriminated whether or not any of the scan registers has an unconnected output terminal; in step SZ
4
, a positive logic output terminal is selected when there is no unconnected output terminal; in step SZ
5
, the unconnected output terminal is selected when there is an unconnected output terminal; in step SZ
6
, the selected output terminal is connected with the scan data input terminal of a scan register at the rear stage; and in step SZ
7
, it is discriminated whether or not all the pairs in the scan chain have been processed.
FIG. 21
is a circuit diagram of a semiconductor integrated circuit before connecting scan registers. In
FIG. 21
, a reference numeral
20
B denotes an area for forming the semiconductor integrated circuit before the formation of a scan chain, reference numerals
21
through
25
denote scan registers working as shift registers during the scan test, reference numerals
26
through
32
denote AND gates for outputting “1” merely when two input signals are both “1”, reference numerals
33
through
35
are inverters each for outputting an inverted signal of an input signal, a reference numeral
36
denotes a scan-in terminal for receiving a signal for the scan test, and a reference numeral
37
denotes a scan-out terminal for outputting the signal for the scan test. The negative logic output terminal NQ of the scan register
22
and the positive logic output terminal Q of the scan register
25
are not used in the normal operation mode and are unconnected.
FIG. 26
is a circuit diagram obtained by conducting the allocating and interconnecting procedures of
FIG. 25
on the semiconductor integrated circuit of FIG.
21
. In
FIG. 26
, a reference numeral
20
A denotes an area for allocating the semiconductor integrated circuit after the formation of the scan chain, wherein the positions and the dimensions of respective elements and wires reflect those of actual hardware. Reference numerals
21
through
37
are used to refer to the same composing elements shown in FIG.
21
and the description is omitted. A reference numeral
41
Z denotes a wire for connecting the scan register
21
and the scan register
22
, a reference numeral
42
Z denotes a wire for connecting the scan register
22
and the scan register
23
, a reference numeral
43
Z denotes a wire for connecting the scan register
23
and the scan register
24
, a reference numeral
44
Z denotes a wire for connecting the scan register
24
and the scan register
25
, and a reference numeral
45
Z denotes a wire for connecting the scan register
25
and the scan-out terminal
37
.
Now, specific procedures for connecting the respective scan registers by conducting the respective steps of
FIG. 25
on the semiconductor integrated circuit before the formation of the scan chain shown in
FIG. 21
will be described. First, in step SZ
1
, it is specified that the scan registers are connected in the order of the scan register
21
, the scan register
22
, the scan register
23
, the scan register
24
, the scan register
25
and the scan-out terminal
37
.
Next, in step SZ
2
, the scan register
21
and the scan register
22
are selected as a first pair.
Then, in step SZ
3
, it is discriminated whether or not the positive logic output terminal Q or the negative logic output terminal NQ of the scan register
21
is unconnected. In this case, there is no unconnected terminal, and hence, the procedure proceeds to step SZ
4
.
Next, in step SZ
4
, the positive logic output terminal Q is selected, and in subsequent step SZ
6
, the selected positive output terminal Q is connected with the scan data input terminal SI of the scan register
22
through the wire
41
Z.
Then, in step SZ
7
, since there remain other pairs of the scan registers, the procedure returns to step SZ
2
.
Subsequently, in step SZ
2
, the scan register
22
and the scan register
23
are selected as a next pair. In step SZ
3
, the negative logic output terminal NQ of the scan register
22
is discriminated to be unconnected, and hence,
Ichinomiya Takahiro
Motohara Akira
Takeoka Sadami
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Phan Thai
Teska Kevin J.
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