Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-12-23
2001-08-21
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S295000, C257S344000, C257S412000
Reexamination Certificate
active
06278164
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor apparatus and a manufacturing method therefor, and more particularly to a semiconductor apparatus which incorporates a gate electrode having its side and bottom surfaces covered with gate insulator films, and a manufacturing method therefor to which a high temperature treatment is applicable.
This application is based on Japanese Patent Application No. 8-356493, filed on Dec. 26, 1996, the contents of which is cited herein by reference.
In a MOS (metal oxide semiconductor) transistor using a SiO
2
film as a gate oxide film, it is important to thin the gate oxide film more than ever, in order to enhance the performance of the short channel transistor. It is considered, however, a problem in practical use to thin the gate oxide film by more than a thickness (e.g. about 3 nm or less) at which direct tunneling will occur.
As a method for solving the problem, it is proposed to form the gate oxide film of a so-called “high dielectric film” (such as a Ta
2
O
5
film) in place of the SiO
2
film, in order to reduce the SiO
2
equivalent film thickness and at the same time to restrain a leak current (due to direct tunneling) between the gate electrode and the substrate or a source and drain region of the transistor.
If in the transistor using the high dielectric film, however, a high temperature step ranging from 800-1000° C. (including an annealing step to activate a source/drain ion implantation layer, a step for reflowing an interlayer film, etc.) is performed after the high dielectric film as the gate oxide film and a gate electrode made of a metal are formed, interface reaction will occur between Si substrate and the high dielectric film or between the high dielectric film and the gate electrode. Therefore, it is difficult for the transistor with the high dielectric film to endure the high temperature step, and the high dielectric film may well degrade. Accordingly, a transistor of high electric characteristics is hard to obtain.
Referring to
FIGS. 1A and 1B
, the above-described conventional problems will be explained in more detail. In these figures, reference numeral
31
denotes a silicon substrate, reference numeral
32
an element isolating region formed by the STI (Shallow Trench Isolation), reference numeral
33
a gate insulating film, reference numeral
34
a gate electrode, and reference numeral
35
a source/drain layer.
If, for example, the source/drain layer
35
is formed before the gate electrode
34
, to protect the gate electrode
34
from a heat treatment performed for obtaining the layer
35
, it is possible that the source/drain layer
35
will not be aligned with the gate electrode
34
as shown in FIG.
1
A. This is a serious problem. Further, it must be considered how to execute, during a flattening step, a heat treatment such as a reflowing treatment to be performed after the gate electrode
34
is formed.
On the other hand, when the gate electrode
34
is formed before the source/drain layer
35
as in the prior art, it is necessary to form a gate insulator film
33
by interposing a high dielectric film between SiO
2
films as shown in
FIG. 1B
, in order to enable the gate electrode to endure a high temperature step such as a step for activating the source/drain layer
35
or for reflowing the interlayer film. Thus, the total thickness of the gate insulator film inevitably increases.
In addition, to increase the breakdown voltage between the gate electrode
34
and the source/drain layer
35
and to enhance the reliability of the element, post-oxidation is generally performed after the gate electrode
34
is formed. The composition of the high dielectric film changes after the post-oxidation step (performed at, for example, about 900° C. for about 30 minutes), with the result that the leak current of the gate insulator film
33
may well increase, which means degradation in the characteristics of the gate insulator film.
As described above, where a high dielectric film is used as the gate insulator film, it may well degrade since it does not have a heat resistance sufficient for a high temperature treatment required to form the semiconductor apparatus. Accordingly, a transistor of excellent electric characteristics is hard to obtain.
BRIEF SUMMARY OF THE INVENTION
It is the object of the invention to provide a semiconductor apparatus in which a high dielectric film or a ferroelectric film can be used as a gate insulator film, and a high temperature treatment is not necessary, and also provide a method for manufacturing the semiconductor apparatus.
According to a first aspect, there is provided a semiconductor apparatus comprising: a substrate with a source/drain region formed therein; a gate electrode provided above the substrate; and a gate insulator film covering bottom and side surfaces of the gate electrode.
The semiconductor element includes an element of a transistor structure having a source, a drain and a gate, such as an MIS transistor, a ferroelectric memory element, etc.
Since in this structure, the bottom and side surfaces of the gate electrode are covered with the gate insulator film, a sufficient breakdown voltage can be secured between the gate electrode and the substrate or between the gate electrode and the source/drain region, without post-oxidation performed in the conventional case. Moreover, the gate insulator film is provided also on the side surfaces of the gate electrode, which enables the channel length of the semiconductor element to be made shorter by twice the thickness of the gate insulator film than a minimum value limited by the lithography. In addition, since a depression which will be formed at a corner during the STI is filled with the gate insulator film, formation of a parasitic transistor at the corner can be restrained, thereby reducing the range of variations in threshold voltage of a MOS transistor, etc. It is preferable that the gate insulator film on the bottom and side surfaces of the gate electrode has a substantially uniform thickness. To this end, the gate insulator film is formed by, for example, the CVD (Chemical Vapered Deposition) method.
According to a second aspect of the invention, there is provided a method for manufacturing a semiconductor apparatus comprising the steps of: forming a dummy gate pattern on a semiconductor substrate; implanting an impurity into the semiconductor substrate, using the dummy gate pattern as a mask, to form a source/drain region; forming an insulator film on side surfaces of the dummy gate pattern; removing the dummy gate pattern; forming a gate insulator film on bottom and side surface of a groove formed by the removal of the dummy gate pattern; and filling a conductive material into the groove covered with the gate insulator film to form a gate electrode.
According to a third aspect of the invention, there is provided a method for manufacturing a semiconductor apparatus comprising the steps of: forming first and second dummy gate patterns on a semiconductor substrate; implanting an impurity into the semiconductor substrate, using the dummy gate patterns as masks, to form source/drain regions; forming insulator films on the side surfaces of the first and second dummy gate patterns; removing the first dummy gate pattern, and forming a first gate insulator film on bottom and side surface of a first groove formed by the removal of the first dummy gate pattern; removing the second dummy gate pattern, and forming a second gate insulator film on bottom and side surface of a second groove formed by the removal of the second dummy gate pattern; and filling a conductive material into the first and second grooves covered with the first and second gate insulator films, to form first and second gate electrodes, respectively.
In the method of the invention, various high temperature treatments such as activation of an impurity implanted in the source/drain region can be performed before the gate electrode and the gate insulator film are formed, thereby preventing the gate insulator film (in particular, if the gat
Aoyama Tomonori
Hieda Katsuhiko
Imai Keitaro
Tsunashima Yoshitaka
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Loke Steven
Vu Hung Kim
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