System for sharing data buffers from a buffer pool

Details System for sharing data buffers from a buffer pool System for sharing data buffers from a buffer pool

1998-07-30

2001-08-28

Beausoleil, Robert (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S120000, C710S120000

Reexamination Certificate

active

06282589

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to computer systems, and more particularly, to an apparatus and method for sharing buffers between bus interfaces and a computer.
2. Description of the Related Technology
Conventional personal computer systems include a processor for processing data, one or more system controllers for controlling data flow between computer buses, and one or more bus bridge circuits for controlling data flow between various bus types within the computer system. In many conventional computer systems, the processor and system controller are controlled by a first clock while the bus bridge and bus components are controlled by a second clock.
For example, an Intel Pentium Microprocessor and its corresponding system controller may be controlled by a 200 MHz clock while the bus bridge circuit may be controlled by a 33 MHz clock. Because of the difference in clock speeds between these components, many computer systems incorporate a series of buffers to manage data transfers from components from one clock domain to components in another clock domain.
In conventional computer systems, a fixed number of data buffers are integrated into the system controller and bus controllers to buffer data transfers between clock domains. For example, many system controllers include a plurality of first-in, first-out data buffers to manage data transfers to/from a Peripheral Component Interconnect (PCI) device and the processor. Similarly, a conventional system controller may employ a plurality of first-in, first-out data buffers to buffer transfers between the processor and the memory subsystem. Other buffers may be located along the memory address bus to buffer transfers from the computer main memory to devices on the PCI bus. Thus, in all, a system controller may incorporate numerous individual buffers, with each buffer being only connected to a particular source and target component.
Although this structure ensures that each data path between clock domains includes a buffer, it leads to an inefficient use of data registers within the system controller. It would be a rare occasion that every data path within a system controller should need a buffer at the same time. Thus, it would be more advantageous to provide a mechanism wherein the data path transferring the greatest amount of data is always provided with a large set of buffers while the data path transferring the smallest amount of data is provided with a minimum amount of buffers.
U.S. Pat. No. 4,158,235, to Call, et al. discloses a buffer pool system that supports bi-directional data transfers between multiple data ports. The Call, et al. buffer pool system includes a control unit and a plurality of individual buffer units wherein each buffer unit has a fixed size. However, in the Call, et al. system, a buffer full status signal indicates that all of the buffers in the buffer pool are full, but does not use a pre-allocation system to identify if particular ports are empty or full. In addition, the Call, et al. system does not allow for concurrent transfers from various components to the buffer pool because of serial arbitration through the control bus. Thus, the state of the art needs a buffer pool system with a higher degree of concurrency to handle data transfers more efficiently.
The strategy in conventional computer systems of providing dedicated buffers for each data path results from a desire to ensure that buffer space is always available for data transfer operations. However, this strategy also requires extensive buffer space for each data path so that consecutive large data transfer operations can be accommodated. Moreover, as bus architecture complexity and operational speed increases, the need for extensive buffering likewise increases. Moreover, because buffer circuits are often integrated into an application specific integrated circuit die, extensive buffering requires additional space on the die, which increases the cost considerably.
However, in practice, the simultaneous need for a plurality of data paths, each having extensive buffer space, is rare because data buffer use is often mutually exclusive. Thus, providing extensive buffer space for each input or output data path wastes a considerable amount of the provided buffer storage space. Furthermore, the wasted buffer space is cumulative since most computer systems include a plurality of interfaces for communicating with numerous peripheral and I/O devices coupled to their respective buses. To enable data transfer between high and low speed components without delaying the high speed components, computer manufacturers require cost effective methods and technologies to increase the efficiency and utilization of buffer storage space.
SUMMARY OF THE INVENTION
One embodiment of the invention is a system for buffering data transfers between components in a computer system. The system includes a plurality of buffers; a first pointer referencing the address of a computer component; a second pointer referencing at least one buffer in the plurality of buffers; and a translation table, wherein the translation table comprises entries correlating the value of the first pointer with the value of the second pointer.
Another embodiment of the invention is a system in a computer for transferring data from a first clock domain to a second clock domain. The system comprises a first pointer in communication with a first component in the first clock domain and with a plurality of buffers; a table in communication with the plurality of buffers, said table comprising a plurality of storage locations; a first storage location in the table for storing the value of the pointer; a second storage location in the table for storing a reference to one or more buffers in the plurality of buffers; and a third storage location in the table for storing the port value of the first component.
Yet another embodiment of the invention is a computer system that includes a processor; a first pointer in communication with said processor and with a plurality of buffers; and a table in communication with the plurality of buffers, said table comprising a plurality of storage locations; a first storage location in the table for storing the value of the pointer a second storage location in the table for storing a reference to one or more buffers in the plurality of buffers
Still another embodiment is a system in a computer for transferring data in the computer, comprising: means for providing the address of data to be transferred; means for allocating a buffer from a plurality of buffers to temporarily store said data; means for transferring the data from the provided address to the allocated buffer.
One other embodiment is a programmable storage device having instructions that, when executed, perform the method of:
providing an address identifying a location of data to be transferred;
allocating a buffer from a plurality of buffers to temporarily store said data; and
transferring the data from the location identified by the provided address to the allocated buffer.


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