Structure for transistor devices in an SRAM cell

Details Structure for transistor devices in an SRAM cell Structure for transistor devices in an SRAM cell

1996-09-12

1998-10-20

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257379, 257903, 257904, H01L 2976, H01L 2994, H01L 31062

Patent

active

058250700

ABSTRACT:
An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The SRAM memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node. The first and second transfer gate transistors each include a gate oxide layer having a first thickness, and the first and second pull-down transistors each include a gate oxide layer having a second thickness, wherein and the first thickness is different from the second thickness.

REFERENCES:
patent: 4866002 (1989-09-01), Shizukuisha et al.
patent: 5285096 (1994-02-01), Ando et al.
patent: 5373170 (1994-12-01), Pfiester et al.

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