Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-04-30
2001-07-03
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S382000, C257S412000, C257S413000
Reexamination Certificate
active
06255701
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having local wiring (local interconnection) formed by a salicide technology and a method of manufacturing the same.
2. Description of Related Art
For example, miniaturization of a MOS transistor causes a delay due to an increase in resistance of an impurity diffused layer, which constitutes a source region or a drain region (source/drain region) of the transistor, relative to a channel resistance. As means for solving this problem, a MOS transistor which uses the salicide technology has been developed.
A salicide MOS transistor is a transistor in which, in order to decrease the resistance, a metal silicide is formed in a self-aligning manner on the surfaces of a polysilicon layer which constitutes a gate electrode, and an impurity diffused layer which constitutes a source/drain region.
For the salicide MOS transistor, the technology of forming a local interconnection simultaneously with the formation of the metal silicide layer is known. Examples of such technologies include a method in which a film of a high-melting-point metal nitride formed simultaneously with the formation of a high-melting-point metal silicide layer is used as a local interconnection, a method in which a high-melting-point metal layer which can form a silicide is deposited, and an amorphous silicon layer is then formed, followed by heat treatment to form a silicide layer.
FIGS. 17
to
20
are sectional views schematically showing in turn the steps of the latter method. In this method, as shown in
FIG. 17
, a titanium layer
210
is first formed on a silicon substrate
10
having MOSFET
100
formed thereon, as in a usual salicide process. The titanium layer
210
is formed over the entire region including source/drain regions
12
a
and
12
b
, a gate electrode
16
and a side wall insulating layer
18
, which constitute the MOSFET
100
. As shown in
FIG. 18
, an amorphous silicon layer is then formed on the surface of the titanium layer
210
, followed by usual photolithography and dry etching to form an amorphous silicon layer
80
patterned in the predetermined plane form of a local interconnection. As shown in
FIG. 19
, heat treatment is performed for forming a silicide, and unreacted portions of the amorphous silicon layer and the titanium layer are removed by wet etching. In this step, titanium silicide layers
22
a
and
22
b
are formed on the source/drain regions
12
a
and
12
b
, and the gate electrode
16
, and a local interconnecting layer
22
c
for connecting one of the source/drain regions
12
b
and the gate electrode
16
is formed. As shown in
FIG. 20
, an interlayer insulating film
30
is formed, a contact hole
30
a
is formed at a predetermined position, and a metallic interconnecting layer
32
is formed.
In the above-mentioned conventional method, since the local interconnecting layer
22
c
comprises a metal silicide (titanium silicide) in which impurities are easily diffused, the impurity concentration of the source/drain region
12
b
easily changes by the diffusion of impurities. Namely, this method has the problem of causing variations in the threshold value due to the diffusion the impurities to the source/drain region
12
b
through the local interconnecting layer
22
c
, and the problem of easily increasing a contact resistance and a junction leak due to a decrease in the impurity concentration.
The technology of forming a local interconnection by using a titanium nitride film, as disclosed in U.S. Pat. No. 4,746,219 causes no diffusion of impurities through the local interconnection, but has the problem of having the high electric resistance of the local interconnection.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device and a method of manufacturing the same which can prevent impurity diffusion and which has a low-resistance local interconnection.
A semiconductor device of the present invention comprises a local interconnecting part for electrically connecting a silicon-containing first layer and a silicon-containing second layer, wherein the local interconnecting part comprises a first metal silicide layer formed in a self-aligning manner on the surface of the first layer, a second metal silicide layer formed in a self-aligning manner on the surface of the second layer, and an interconnecting part for electrically connecting the first metal silicide layer and the second metal silicide layer, the interconnecting part comprising a single metallic layer or a plurality of metallic layers as a component. Alternatively, the interconnecting part comprises a barrier layer formed in contact with at least the first and second metal silicide layers, and a conductive layer having a lower resistance than the barrier layer.
In the present invention, since the local interconnecting part for electrically connecting the first metal silicide and the second metal silicide has the interconnecting part comprising the metallic layer or the barrier layer and the conductive layer, the present invention has the following functions:
a. Since n-type and p-type impurities hardly diffuse in the metallic layer or the barrier layer which constitutes the interconnecting part, the impurity concentration of a layer having a defined silicon concentration, for example, a source or drain region of a MOS transistor, is not changed, thereby causing neither variation in the threshold value due to counter doping nor increase in contact resistance and junction leak due to a decrease in impurity concentration.
b. Since the interconnecting part comprises the conductive layer composed of a metal or the like, the electric resistance can be decreased, as compared with a conventional titanium nitride layer.
In addition, the use of local interconnection for a connecting structure makes unnecessary an interconnecting layer through a contact hole, and thus permits an attempt to increase the degree of integration of a pattern layout.
Examples of a semiconductor device comprising combination of the silicon-containing first layer and second layer which are connected by the local interconnecting part include the following:
A. A semiconductor device in which the first and second layer are formed in a region of the same element and contain the same type of impurity, the first layer comprises an impurity-diffused layer formed on a main surface of a semiconductor substrate, and the second layer comprises an interconnecting layer formed on the semiconductor substrate through at least an insulating layer and containing the same type impurity as the impurity-diffused layer.
A typical example of such a semiconductor device is a MOS element. The first layer comprises an impurity-diffused layer which constitutes a source or drain region, and the second layer comprises a gate electrode.
B. A semiconductor device in which the first layer is a first conduction type impurity-diffused layer formed in a region of a first element on a main surface of a semiconductor substrate, and the second layer is a second conduction type impurity-diffused layer formed in a region of a second element on a main surface of the semiconductor substrate.
A typical example of such a semiconductor device is a CMOS element. The first layer is an n-type impurity-diffused layer which constitutes a source or drain region of a NMOS element, and the second layer is a p-type impurity-diffused layer which constitutes a source or drain region of a PMOS element.
C. A semiconductor device in which the first layer is an interconnecting layer formed in a region of a first element on a main surface of a semiconductor substrate at least through an insulating layer and containing a first conduction type impurity, and the second layer is an interconnecting layer formed in a region of a second element on a main surface of the semiconductor substrate at least through an insulating layer and containing a second conduction type impurity.
A typical example of such a semiconductor device is a CMOS element. The first layer co
Hogan & Hartson LLP
Loke Steven
Seiko Epson Corporation
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