Method for forming interlayer dielectric layer

Details Method for forming interlayer dielectric layer Method for forming interlayer dielectric layer

1999-10-28

2001-05-29

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S626000, C438S631000, C438S633000, C438S634000, C438S692000, C438S697000, C438S699000

Reexamination Certificate

active

06239020

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88114374, filed Aug. 23, 1999.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating an interlayer dielectric layer on a semiconductor substrate. More particularly, the present invention relates to a method for planarizing the interlayer dielectric layer on a semiconductor substrate.
2. Description of Related Art
In the structure of a semiconductor substrate with memory devices, such as dynamic random access memory (DRAM), the height variation between the memory cell region and periphery circuit region is big. The variation of height is caused by the enlargement of the surface of the bottom electrode at the memory cell for increasing the capacitance to a level sufficient to satisfy circuit demand. Therefore, the height of the bottom electrode causes the height variation between the memory cell region and periphery circuit region.
The big height variation between the memory cell region and the periphery circuit region will result in a poor pattern transfer for a metal interconnect in subsequent processing. Therefore, before fabricating the metal interconnect, the interlayer dielectric layer (ILD) should be planarized.
Conventionally, a planarized interlayer dielectric layer is fabricated by depositing boro-phosphosilicate glass (BPSG) with flowability on the surface of semiconductor devices and then chemical mechanical polishing (CMP) the BPSG layer. However, the planarized surface is only in the memory cell region or in the periphery circuit region, so the height variation between the memory cell region and the periphery circuit region is still significant.
FIGS. 1A
to
1
B schematically illustrate a conventional method for fabricating an interlayer dielectric layer on a semiconductor substrate. As shown in
FIG. 1A
, a semiconductor substrate
100
having a memory cell region
100
a
and a periphery circuit region
100
b
is provided. Semiconductor devices, such as capacitors or transistors have been formed on the semiconductor substrate.
FIGS. 1A
to
1
B only show the height variation between the memory cell region
100
a
and the periphery circuit region
100
b
; the detailed arrangement of the semiconductor devices is not shown.
A silicon oxide layer
102
and boro-phosphosilicate glass (BPSG) layer
104
are deposited on the semiconductor substrate
100
by conventional chemical vapor deposition. The primary planarization on the memory cell region
100
a
and periphery circuit region
100
b
is provided by the flowability of the BPSG layer
104
.
Referring to
FIG. 1B
, a chemical mechanical polishing (CMP) process is executed on the BPSG layer for further planarization of the same. Then, an oxide layer
106
is blanket-formed on BPSG layer
104
to cover up the damage thereon caused by CMP process. Therefore, a planarization of the interlayer dielectric layer is obtained only at the memory cell region
100
a
or the periphery circuit region
100
b
. However, the height variation between the memory cell region
100
a
and periphery circuit region
100
b
is still significant.
In addition, in the above-mentioned conventional method, the polishing of BPSG layer is controlled by the operation time. Therefore, it is not easy to control the polishing level of BPSG. Furthermore, due to the height difference between the memory cell region and the periphery circuit region on the semiconductor substrate, the polishing rate thereon is different so as to result in poor uniformity.
SUMMARY OF THE INVENTION
In one aspect, the present invention provides a method for fabricating an interlayer dielectric layer on a semiconductor substrate with a memory cell region and a periphery circuit region, such that the two regions together are nearly planar.
In another aspect, the present invention provides a method for fabricating an interlayer dielectric layer on a semiconductor substrate with a memory cell region and a periphery circuit region with excellent uniformity.
In still another aspect, the present invention provides a method for fabricating an interlayer dielectric layer on a semiconductor substrate with a memory cell region and a periphery circuit region, wherein a stop layer is provided during the operation of CMP on the interlayer dielectric layer. Therefore, the process window for fabricating the interlayer dielectric layer is enlarged.
In yet another aspect, the present invention provides a method for fabricating an interlayer dielectric layer on a semiconductor substrate with a memory cell and a periphery circuit region, the yield of which is increased.
According to the present invention, a method for fabricating an interlayer dielectric layer on a semiconductor substrate with a memory cell region and a periphery circuit region is disclosed, wherein semiconductor devices are formed on the memory cell region and the periphery circuit region so as to result in a height variation therebetween. The present method comprises the steps of forming a first dielectric layer blanket-covering the semiconductor substrate, wherein a first height variation exists between the memory cell region and the periphery circuit region. Then, a stop layer is conformally blanket-formed on the first dielectric layer. Next, a second dielectric layer is formed on the stop layer. A chemical mechanical polishing process is executed on the second dielectric layer until the stop layer on the memory cell region is exposed. This formation of the structure of a first dielectric layer/stop layer/second dielectric layer is repeated at least two times to achieve a planarized interlayer dielectric layer. A cap layer is formed on the top surface of the planarized interlayer dielectric layer.
In accordance with one embodiment of the present invention, the chemical mechanical polishing process is executed on the second dielectric layer to expose the stop layer on the memory cell region of the semiconductor substrate, while part of the second dielectric layer remains on the periphery circuit region. Hence, a second height variation between the memory cell region and the periphery circuit region is formed, wherein the second level difference is less than the first level difference.
Furthermore, in accordance with one embodiment of the present invention, the process route, formation of the structure of a dielectric layer/stop layer/dielectric layer and the execution of the CMP on the upper dielectric layer, is performed two times.


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