Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-06-09
2001-01-30
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S335000, C257S368000, C257S409000, C257S630000
Reexamination Certificate
active
06180981
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor devices and, more specifically, to a termination structure for semiconductor devices, such as MOS gate controlled (“MOS-gated”) semiconductor devices.
MOS-gated devices are well known in the art and include devices such as the MOS-gated devices shown in U.S. patent application Ser. No. 08/299,533, filed Sep. 1, 1994 (IR-1113), the subject matter of which is incorporated herein by reference. MOS-gated devices also include power MOSFETs, MOS-gated thyristors, gate turn-off devices and the like.
The MOS-gated devices are typically formed of a plurality of active cells which include cells located at the periphery of the die. The peripheral cells, when subject to the full source-to-drain voltage, are prone to avalanche breakdown between the outermost portion of the cell and the adjacent street.
It is therefore necessary to provide a device structure that prevents breakdown at the active peripheries of the chip.
The manufacturing process for devices that include such structures includes a number of photolithographic masking steps and critical mask alignment steps each of which adds manufacturing time and expense as well as provides possible sources of device defects.
It is therefore also desirable to employ a termination structure that occupies a minimum surface area of the chip and does not require added masking steps.
SUMMARY OF THE INVENTION
The present invention provides for a termination structure that terminates the active peripheries of a semiconductor device to prevent breakdown at the peripheries of the device. A field plate is formed of the same polysilicon layer that forms the gate electrode and changes the curvature of the electric fields generated at the edge of the diffusion regions.
An aspect of the present invention relates to a termination structure for a semiconductor device and a process for fabricating the termination structure. A layer of field insulation material is formed atop a silicon substrate. One or more selected regions of the field insulation layer is patterned and etched away to form at least one opening and at least one remaining portion. A polysilicon layer is deposited in the openings and atop the remaining portions of the field insulation material layer, and selected portions of the polysilicon layer are patterned and etched away to form spaced openings. Each of the spaced openings has at least a first part formed in a respective opening of the field insulation material and is adjacent to the field insulation material. A portion of the polysilicon layer that is atop the field insulation layer defines a polysilicon field plate. First diffused regions are formed by introducing impurities of a first conductivity type into silicon substrate surface regions that are located beneath the first part of the openings in the polysilicon layer. Second diffused regions are formed of impurities of a second conductivity type, which is of opposite type to the first conductivity type, and are introduced into the silicon substrate surface regions. The first diffused regions are deeper and wider than the second diffused regions. An overlaying insulation layer is deposited, and then selected portions are patterned and etched away to expose underlying surface regions of the polysilicon field plate and underlying areas of the silicon substrate surface regions. A conductive layer is deposited over the insulation layer and over the underlying polysilicon field plate surface regions and the underlying silicon substrate surface regions. The conductive layer is etched to form one or more electrodes that contact the polysilicon field plate and one or more electrodes which contact the underlying areas of the silicon substrate surface regions.
In accordance with this aspect of the present invention, the polysilicon field plate may overlap the first diffused regions. A polysilicon finger may be formed in a region located between a respective pair of openings in the polysilicon layer. The width of the polysilicon finger may be sufficiently small such that the first diffused regions of a pair of openings overlap.
An opening in the field insulation material may surround the semiconductor device to form a street region, and an equipotential ring may be formed atop the field insulation material and the street region to hold the street region to a predefined potential.
The field insulation material may be isotropically etched to have a sloped edge, and impurities may be introduced through the sloped edge. A polysilicon field plate may extend over the sloped edge of the field insulation material.
The first conductivity type may be P-type and the second conductivity type may be N-type. Alternatively, the first conductivity type is N-type, and the second conductivity type is P-type. The polysilicon field plate may extend over an edge of the layer of field insulation material.
The openings in the polysilicon layer may include a second part that is formed atop the remaining portion of the layer of field insulation material. The field insulation material may be silicon dioxide, and the impurities of first and second conductivity type may be introduced by implanting the impurity into the silicon substrate and then driving in the impurity. The overlaying insulation layer may be a low-temperature oxide layer.
Another aspect of the present invention is a semiconductor device having the termination structure of the present invention and a process for fabricating the semiconductor device. The device and its fabrication process includes a layer of gate insulation material that is formed atop the silicon substrate in at least one opening in the layer of field insulation material. Spaced openings are formed in the polysilicon layer and include peripheral openings that have a first part formed atop the layer of gate insulation material and adjacent to the remaining field insulation material layer. Third diffused regions are also introduced into the silicon substrate surface regions. The second diffused regions have a final depth which is less than that of the third diffused regions, and the first diffused regions are deeper and wider than and have a lower concentration than the third diffused regions. Depressions are etched in the underlying areas of the silicon substrate surface regions and have a depth greater than the depth of the second diffused regions. Further portions of the silicon substrate surface are exposed adjacent to and surrounding the depressions in the underlying areas. The conductive layer comprises at least one gate contact which contacts the polysilicon field plate and at least one source contact which contacts the third diffused regions at the bottom of the depressions and the second diffused regions at the upper portions of the depressions and at the further portions.
In accordance with this aspect of the present invention, the gate insulation material may be silicon dioxide, and the polysilicon field plate may extend over a portion of the gate insulation layer.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
The invention will now be described in greater detail in the following detailed description with reference to the drawings in which:
FIG. 1
shows a top view of an MOS-gated device according to an embodiment of the present invention;
FIG. 2
shows the cell topology of the surface of a known MOS-gated device;
FIG. 3
shows a cross-sectional view of the MOS-gated device of
FIG. 2
taken across section line
2
—
2
;
FIG. 4
shows the cell topology of a portion of the outermost active cells and the termination region of the MOS-gated device of
FIG. 1
;
FIG. 5
shows a cross-sectional view of the MOS-gated device of
FIG. 4
taken across section line
5
—
5
;
FIG. 6
shows a cross-sectional view of the MOS-gated device of
FIG. 4
taken across section line
6
—
6
;
FIG. 7
shows a cross-sectional view of a region of the MOS-gated device of
FIG. 1
whi
Kinzer Daniel M.
Wagers Kenneth
Chaudhuri Olik
International Rectifier Corp.
Ostrolenk Faber Gerb & Soffen, LLP
Pham Hoai
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