Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-06-30
2001-09-25
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06295628
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of optimizating logic synthesis, and more particularly to a method of logic synthesis using common and similar circuit extraction applicable to a large scale integrated circuit.
One of the conventional logic synthesis techniques is an operator sharing method wherein hardware descriptions at a resistor transfer level and operations not commonly executed are commonly held by switching with a multiplexer to reduce the number of the necessary arithmetic logic circuits.
Japanese laid-open patent publication No. 2-171862 discloses that common parts in the descriptions are extracted and defined as function macros and then transformed into a common reference form at a hierarchically low level so that an optimization process is executed only at the hierarchically low level to shorten the optimization processing time. Other cases are not commonly optimized even when a plurality of similar circuits exist.
In the above operator sharing system, arithmetic operations and hardware functions to be concurrently executed are not common subject matter. This means that it is impossible to shorten the optimization processing time.
The logic synthesis disclosed in the Japanese laid-open patent publication No. 2-171862 has an object to obtain simple and clear synthesis results in the circuit-divisional. method but is not intended to prevent deterioration of the optimization performance.
In the optimization processes, there are processes for which boundary conditions should be considered. The boundary conditions are largely different for every instance and optimal results might be not obtainable simply with reference to the hierarchically low level.
In the general logic synthesis other than the above, when a plurality of similar partial circuits exist in a large scale integrated circuit, various optimization processes are made to each partial circuit without common processing. This needs a long time for processing.
In the above circumstances, it had been required to develop a novel logic synthesis apparatus and method of logic synthesis wherein common and similar partial circuits are extracted from a large scale integrated circuit to shorten an optimization processing time without deterioration of optimization performance.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel logic synthesis apparatus free from the above disadvantages.
It is a further object of the present invention to provide a novel logic synthesis apparatus, wherein common and similar partial circuits are extracted from a large scale circuit to shorten optimization processing time without. deterioration of optimization performance.
It is furthermore an object of the present invention to provide a novel method of logic synthesis free from the above disadvantages.
It is still a further object of the present invention to provide a novel method of logic synthesis, wherein common and similar partial circuits are extracted from a large scale circuit to shorten optimization processing time without deterioration of optimization performance.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.
In order to achieve the above objects, a novel logic synthesizer comprises a circuit analyzer for reading hardware function operation descriptions in hardware description language to translate the same into internal circuit expressions, a memory for storing circuits, common part information and restriction information, a hierarchically low level separator for separating hierarchically low level information being commonly referred, an output device for outputting a synthesis result, an optimization device for optimization process, and a restriction condition input device for inputting restriction conditions, wherein the circuit analyzer comprises a basic analyzing device for basic analysis of the hardware descriptions, a similar description extraction for extracting common and similar descriptions and a hierarchically low level common device for translating the extracted common descriptions into common reference form at a hierarchically low level.
A novel method of optimization of logic synthesis comprises the steps of inputting hardware function operation descriptions in hardware description language, extracting common logics from the inputted logical information to translate the common logics into a common reference form at a hierarchically low level, merging common logics including common inputs, executing a first logical optimization for common logics extracted, separating the first optimized common logics, and executing a second logical optimization to the separated common logics.
REFERENCES:
patent: 4882690 (1989-11-01), Shinsha et al.
patent: 5402357 (1995-03-01), Schaefer et al.
patent: 5416719 (1995-05-01), Pribetich
patent: 5436849 (1995-07-01), Drumm
patent: 5572437 (1996-11-01), Rostoker et al.
patent: 5721690 (1998-02-01), Asaka
patent: 5726902 (1998-03-01), Mahmood et al.
patent: 5751596 (1998-05-01), Ginetti et al.
patent: 5856926 (1999-01-01), Matsumoto et al.
patent: 6-259497 (1994-09-01), None
patent: 7-334539 (1995-12-01), None
NEC Corporation
Siek Vuthe
Smith Matthew
Young & Thompson
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