Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-03-29
2001-05-01
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S750000, C257S786000
Reexamination Certificate
active
06225697
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same and more particularly to the semiconductor device and the method for manufacturing the same in which wiring capacitance between adjacent wirings can be effectively reduced in a wiring structure having a dummy wiring required for planarization of an interlayer dielectric.
2. Description of the Related Art
In an LSI (Large Scale Integrated circuit) used as a microprocessor, a memory or a like semiconductor device, as its integration degree is improved, each of implemented devices is being scaled down in dimension to meet a requirement for smaller devices. Moreover, a semiconductor area in which devices are mounted is becoming smaller in depth and a contact hole formed in an interlayer dielectric is also becoming smaller in size as well. Thus, a scale-down of wiring in semiconductor devices is unavoidable.
A wiring structure allowing the scale-down of the wiring called a “damascene” structure is disclosed in, for example, Japanese Laid-open Patent Application No. Hei10-284600 in which a trench for wiring is formed in the interlayer dielectric in which a conductor is embedded.
FIG. 8
is a plan view of a conventional semiconductor device having the damascene wiring structure described above.
FIG. 9
is a cross-sectional view of the conventional semiconductor of
FIG. 8
taken along a line C—C. In
FIGS. 8 and 9
, on a P-type silicon substrate
51
is formed an N-type source area
52
and a drain area
53
, either of which serves selectively as a device area. A gate electrode
56
composed of a polycrystalline silicon is formed on a channel area
54
disposed between the N-type source area
52
and the drain area
53
. An overall surface of the P-type substrate
51
including that of the gate electrode
56
is covered by a first interlayer dielectric
57
composed of a silicon oxide film to form a MOS (Metal Oxide Semiconductor)-type transistor.
First wiring
58
composed of two or more wirings
58
A,
58
B,
58
C, . . . , disposed in proximity to each other, is formed on the first interlayer dielectric
57
and second wiring
59
composed of a single band-shaped wiring is formed flatly in parallel to the first wiring
58
with a second interlayer dielectric disposed between the first wiring
58
and the second wiring
59
. These first wiring
58
and second wiring
59
are formed so as to be of the damascene structure as described above and they constitute a first layer wiring embedded in trenches for wiring
61
formed in a second interlayer dielectric
60
composed of silicon oxide films. A part of the first wiring
58
communicates with the N-type source area
52
or the drain area
53
through a plug conductor
62
formed in the first interlayer dielectric
57
. The first wiring
58
is so formed that a space between two or more wirings constituting the first wiring
58
is dense, i.e., so-called wiring density is large by implementing two or more wiring
58
A,
58
B,
58
C, . . . so as to be placed in proximity of each other, while the second wiring
59
is so formed that its wiring placement is sparse, i.e., only a single wiring is formed.
A surface of the second interlayer dielectric
60
is planarized by a CMP (Chemical Mechanical Polishing) method. However, at the time of the CMP treatment, an occurrence of erosion
67
on the surface of the second interlayer dielectric
60
of the first wiring
58
is unavoidable, as described later.
A third interlayer dielectric
63
composed of silicon oxide films or the like is formed on the second interlayer dielectric
60
so as to cover overall surfaces of the first layer wiring composed of the first wiring
58
and the second wiring
59
and therefore the above-described MOS-type transistor is protected from outside environments.
FIGS. 10A
to
10
E are process diagrams showing a method for manufacturing the conventional semiconductor device in order of processes.
As shown in
FIG. 10A
, the N-type source area
52
and the drain area
53
, either of which serves selectively as the device area, a gate oxide film
55
and the gate electrode
56
are formed on, for example, the P-type silicon substrate
51
, by using a known photolithography method, ion implantation method or a like. Next, by using a CVD (Chemical Vapor Deposition) method or a like, the first interlayer dielectric
57
composed of a silicon oxide film or a like is grown thereon to form the MOS-type transistor. As shown in
FIG. 10B
, a contact hole is formed on the first interlayer dielectric
57
and then polycrystalline silicon or a like is embedded in the contact hole to form the plug conductor
62
.
As shown in
FIG. 10C
, after the second interlayer dielectric
60
composed of silicon oxide films is grown on the first interlayer dielectric
57
by the CVD method or a like, trenches
61
for wiring are formed at desired positions by performing patterning on the second interlayer dielectric
60
by the photolithography. Then, as depicted in
FIG. 10D
, after a conductor film
66
composed of copper, aluminum or a like is formed on overall surfaces of the second interlayer dielectric
60
including the trenches
61
for wiring by the CVD method, the surface of the second interlayer dielectric
60
is planarized by the CMP method as shown in FIG.
10
E. As a result, at desired positions on the second interlayer dielectric
60
, are formed the first wiring
58
comprised of two or more band-shaped wirings
58
A,
58
B,
59
C, . . . , and the single band-shaped second wiring
59
, each of them having the damascene wiring structure.
The surface of the second interlayer dielectric
60
of the first wiring
58
is inferior, in terms of strength, to that of the first interlayer dielectric
57
, the circumference of which is surrounded by silicon films being excellent in its strength, of the second wiring
59
. Therefore, at the time of the CMP treatment on the surface of the second interlayer dielectric
60
, since polishing is concentrated on the surface of the second interlayer dielectric
60
of the first wiring
58
, its surface is concavely formed, causing the erosion
67
.
A third interlayer dielectric
63
is then grown on the overall surface of the second interlayer dielectric
60
including that of the first wiring composed of the first wiring
58
and the second wiring
59
to protect the above MOS-type transistor from the outside environment and thus the semiconductor device is obtained.
Such conventional semiconductor devices as shown in
FIGS. 8 and 9
have shortcomings that, since the occurrence of the erosion
67
on the surface of the second interlayer dielectric
60
of the first wiring
58
composed of two or more wirings each being placed tightly as described at the time of the CMP treatment of the second interlayer dielectric
60
is unavoidable, the second interlayer dielectric
60
is inferior in terms of its flatness. If an upper layer wiring is formed on the interlayer dielectric
60
being inferior in terms of flatness, it is clear that failures including deformation, breakage or a like in the upper layer readily occur, thus decreasing reliability in the semiconductor device.
To overcome such shortcomings as described above, a semiconductor device is disclosed in Japanese Laid-open Patent Application No. Hei10-27799 in which a dummy wiring is formed between a first wiring and a second wiring.
FIG. 11
is a top view of the conventional semiconductor device having the dummy wiring described above.
FIG. 12
is a cross-sectional view of
FIG. 11
taken along lines D—D. As shown in
FIGS. 11 and 12
, a plurality of electrically-insulated dummy wirings
68
is formed between the first wiring
58
and the second wiring
59
on the first interlayer dielectric
57
and at areas surrounding the second wiring
59
which is placed loosely in terms of a distance. Same reference numbers in
FIGS. 11 and 12
designate corresponding to those in
FIGS. 9 and 10
and descriptions of them are omitted.
As described a
Clark Sheila V.
McGinn & Gibb PLLC
NEC Corporation
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