Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-09-24
2001-07-10
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S353000, C257S401000
Reexamination Certificate
active
06259135
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and methods of manufacture, and more particularly, to an integrated circuit chip wherein different device widths of MOS transistors are obtained in the same circuit and on the same chip based on the depth of etch in a vertical direction.
2. Description of the Related Art
As very large scale integrated (VLSI) circuits become increasingly smaller, they eventually experience a physical limit set by the lithographic capability of their manufacture. In the past, 3-dimensional (3-D) transistor devices have been proposed to further shrink the packing density of integrated circuits. However, such techniques are very difficult to implement in any circuit other than an uniform array of memory cells. For example, in pitch-limited circuits, that is, the sense amplifier, row decoder, column decoder and other circuit elements needed for a memory integrated circuit can not be shrunk in the same manner as the individual memory cells. Therefore, the memory chip cell packing density can not be scaled down effectively. In implementing smaller cell sizes, such as six or seven times the minimum lithographic feature (6F or 7F square), there is not an overall DRAM chip area savings because the core or pitch limited circuits needed to access the memory cells can not be scaled proportionately when the pitch size is reduced.
SUMMARY OF THE INVENTION
The present invention is a new integrated circuit structure and method of manufacture for integrated circuit devices using 3-dimensional transistors to significantly shrink the pitch limited circuits of an integrated circuit chip. In a first embodiment, a plurality of gate widths can be obtained by forming silicon islands on a silicon substrate. Next, a gate dielectric is formed on the silicon islands followed by placement of gate electrodes upon the dielectric material. By electrically connecting one or more of the gate electrodes, individual transistors may be formed having different gate widths based on the number of gate electrodes connected. The structure of the integrated circuit permits pitch limited circuits to be scaled along with non pitch limited circuits.
In an alternative embodiment, different gate widths can be obtained by forming the silicon islands at a multiple of preselected heights. Different island heights results in varying gate width dimensions. Electrically connecting one or more of gate electrodes results in transistors having different gate widths based on the height of the silicon island. The total packing density of the integrated circuit containing pitch limited and non pitch limited circuits is thus improved.
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Hsu Louis L. C.
Radens Carl J.
C. Li Todd M.
Chaudhuri Olik
International Business Machines - Corporation
Neff Daryl K.
Pham Hoai
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