Semiconductor memory device having improved word line arrangemen

Details Semiconductor memory device having improved word line arrangemen Semiconductor memory device having improved word line arrangemen

1996-04-10

1999-05-11

Crane, Sara

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

365 51, 365 63, 365 72, H01L27/108

Patent

active

059030224

ABSTRACT:
A semiconductor memory device according to the present invention comprises a plurality of word lines constituted by gate wirings, a memory cell array having memory cells selectively arranged at nodes between the plurality of word lines and a plurality of bit lines, the memory cell array having a plurality of subarrays which are divided in a word line arrangement direction, a main row decoder arranged at least one end of the memory cell array in the word line arrangement direction, a plurality of sub-row decoders arranged at least one end of each of the plurality of subarrays, and a first wiring layer formed on a layer above the gate wirings and extending from the sub-row decoder, and the first wiring layer is wired to a position where the subarray is divided by two in the word line arrangement direction to be brought into contact with the gate wiring.

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Masayuki Nakamura, et al., "A 29ns 64Mb DRAM with Hierarchical Array Architecture", 1995 IEEE International Solid-State Circuits Conference Digest of Technical Papers, (pp. 246-247), Feb. 1995.
K. Noda, et al., "A Boosted Dual Word-line Decoding Scheme for 256Mb DRAMs", 1992 Symposium on VLSI Circuits Digest of Technical Papers, (pp. 112-113), 1992.
Tadahiko Sugibayashi, et al., "A 30ns 256Mb DRAM with Multi-Divided Array Structure", 1993 IEEE International Solid-State Circuits Conference, (pp. 50-51), 1993.

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