Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-08-25
2001-01-09
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S409000, C257S488000, C257S340000, C257S365000, C257S331000, C257S333000
Reexamination Certificate
active
06172400
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to metal-insulator-silicon field effect transistors (MISFETS), and more particularly the invention relates to a MISFET or MOSFET having a gate-drain shield positioned adjacent to and coplanar with the gate electrode.
The lateral double diffused metal-oxide-silicon field effect transistor (LDMOS) is used in power amplifiers for wireless applications such as in cellular telephones. The gate-to-drain feedback capacitance (Cgd or Crss) of any MOSFET device must be minimized in order to maximize RF gain and minimize signal distortion. C
gd
is critical since it is effectively multiplied by the voltage gain of the device as follows:
C
effectve
=C
rss
(1+gm R
L
)
where gm is the transconductance and R
L
is the load impedance of the device.
Heretofore the use of a source field plate to improve breakdown characteristics have been proposed for use with a LDMOS transistor. See for example, Okabe et al U.S. Pat. No. 4,172,260 and Adler et al U.S. Pat. No. 5,252,848. In each of these structures the source electrode is extended over the gate electrode and insulated therefrom to provide a Faraday shield. However, such a shield over the gate electrode does not optimize the gate-drain capacitance, C
gd
, since the shield does not effectively screen out the C
gd
component under the gate. Further, both structures require complex processing and are not suitable for use with vertical DMOS devices.
Weitzel U.S. Pat. No. 5,119,149 discloses a two-layered gallium arsenide structure and process in which a shield electrode is positioned adjacent to the gate but is not at the same level as the gate. Thus the gate-drain capacitance under the gate electrode is not optimally reduced. Also, the shield is not self-aligned to the gate and can cause variable shielding due to misalignment.
The present invention is directed to providing a lateral shield in an MOSFET power device including an extended drain MOSFET, a lateral DMOS transistor, and a vertical DMOS transistor using processes which are readily implementable.
SUMMARY OF THE INVENTION
In accordance with the present invention, the gate to drain feedback capacitance of a MOSFET device is reduced without increasing the input capacitance of the device. Reliability is improved by lowering the surface electric field at the gate and reducing hot carrier electron injection to the gate oxide. The linearity of the device can be modulated by voltage biasing a shield electrode adjacent to the gate electrode. Further, fabrication of the device permits low cost and simple processing.
Briefly, in a LDMOS transistor in which a gate electrode is formed on a gate oxide overlying a controlled channel between source and drain regions, a lateral shield is formed between the drain and gate with at least part of the shield formed on the gate oxide layer coplanar with the gate electrode. The shield can comprise the same material as the gate and can be fabricated in self-alignment with the gate to minimize and control shield to gate spacing. A typical shield length can be 0.5 to 5.0 microns with shield to gate spacing of 0.1 to 2.0 microns.
The shield electrode can be connected to AC ground for terminating an electric field from the drain and thereby decouple the gate electrode for reduced C
gd
. Alternatively, the shield electrode can have a DC bias voltage to allow modulation of the device linearity.
The invention and objects and features thereof will be more readily apparent from the following detailed description and dependent claims when taken with the drawings.
REFERENCES:
patent: 4288801 (1981-09-01), Ronen
patent: 4317274 (1982-03-01), Yasunari
patent: 4333225 (1982-06-01), Yeh
patent: 4616340 (1986-10-01), Hayashi et al.
patent: 4928159 (1990-05-01), Mihara et al.
patent: 5237186 (1993-08-01), Nakagawa et al.
patent: 5311052 (1994-05-01), Stengl et al.
patent: 5382826 (1995-01-01), Mojaradi et al.
patent: 5384476 (1995-01-01), Nishizawa et al.
patent: 5430316 (1995-07-01), Contierto et al.
patent: 5445978 (1995-08-01), Yilmaz
patent: 5672526 (1997-09-01), Kawamura
patent: 5714781 (1998-02-01), Yamamoto et al.
patent: 5726463 (1998-03-01), Brown et al.
patent: 5834809 (1998-11-01), Kato et al.
patent: 5912490 (1999-06-01), Hebert et al.
patent: 56-83077 (1981-07-01), None
patent: 56-83076 (1981-07-01), None
patent: 8-213479 (1996-08-01), None
Graf; Modern Dictionary of Electronics; p. 716, 1997.*
Hebert Francois
Ng Sze Him
Fenty Jesse A.
Saadat Mahshid
Spectrian Corporation
Townsend and Townsend / and Crew LLP
Woodward Henry K.
LandOfFree
MOS transistor with shield coplanar with gate electrode does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MOS transistor with shield coplanar with gate electrode, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOS transistor with shield coplanar with gate electrode will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2470393