Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-04-18
2001-03-20
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S206000, C365S230060, C365S103000, C365S104000, C365S185160, C365S185050
Reexamination Certificate
active
06205075
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device for carrying out high-speed read-out of data recorded in memory cells.
2. Description of the Related Art
In general, [0]/[1] binary information, or multi-value information expressed by the voltage level of a gate that employs threshold control to turn a transistor ON/OFF, can be stored in a single transistor in a semiconductor memory device such as a ROM (read only memory).
A plurality of memory cell transistors are formed to a matrix on the semiconductor substrate in the aforementioned semiconductor memory device. Word lines formed in patterns in the matrix rows are connected to a gate, while bit lines formed in patterns in matrix columns are connected to a drain.
When reading out data stored in the memory cells of this semiconductor memory device, the memory cell corresponding to the inputted address signal is selected according to which word and bit lines are activated by decoders. The data recorded in the memory cell corresponding to address is read out by comparing the current flowing to the selected memory cell transistor with the current flowing to a reference memory cell at a sense amplifier.
In the above-described semiconductor memory device, each memory cell transistor is formed to be isolated from the other memory cell transistors on the semiconductor substrate by use of an element separating film. The drain for the memory cell transistor is connected to the bit line, and the source is grounded.
A simple design may be employed for the circuitry required for read out in the semiconductor memory device design as described above. However, for each memory cell transistor, it is necessary to form a contact to the diffusion layer comprising the drain, this contact connecting the diffusion layer and the bit line to be wired. Because of this need to form a contract to the drain diffusion layer, a larger area must be employed for the diffusion layer than would otherwise be required in the transistor design. It therefore becomes difficult to increase the degree of integration in the memory cell transistor of the above-described design.
In order to resolve the deficits present in the structure of this memory cell transistor, it has become the practice to employ a virtual grounding type memory cell transistor design and arrangement that increases the degree of integration in the memory cell.
In other words, a design (sub-bit line, virtual sub-grounding line) is employed in which a common diffusion layer is used to form the drain and source for memory cell transistors that are adjacent to one another in a row, and these diffusion layers are connected in the columns. As a result, each diffusion layer is connected on the matrix, and it is no longer necessary to provide a contact to the area in which the memory cells are formed. Thus, the degree of integration in this memory cell transistor can be increased as compared to the case in which a contact is formed.
The conventional semiconductor memory device employing a virtual grounding type memory cell transistor design as described above will now be explained using
FIGS. 13 and 14
.
FIG. 13
is a block diagram showing the structure of a conventional semiconductor memory device.
FIG. 14
is a conceptual diagram showing the detailed structure of memory cell
16
in FIG.
13
.
In
FIG. 13
, data is stored in memory cell transistors that form a memory cell area
16
B in memory cell
16
. An address AD is input from an external CPU (central processing unit) or the like, specifying a memory cell transistor within memory cell area
16
B. The data stored in this memory cell transistor is then read out as a result.
Address buffer
11
performs waveform shaping of the inputted address signal AD, and, after holding the signal, outputs it to Y decoder
12
, bank decoder
13
, X decoder
4
and virtual GND selector
15
. X decoder
4
decodes part of the plurality of bits in the address AD signal, and selects and activates one word line selection signal from among word line selection signal WD
0
~word line selection signal WDn. As a result, all the memory cell transistors in one row of the memory cell array in memory cell area
16
B are selected together, and a data read out state is enabled.
Y decoder
12
decodes part of the plurality of bits in the address signal AD, and outputs Y decoder signal YD to Y selector
17
. Based on the inputted Y decoder signal YD, Y selector
17
selects one main bit line from among main bit line D
1
~main bit line D
1
that are connected to each memory cell transistor in memory cell
16
.
As a result, a main bit line is connected to sense amplifier circuit
9
, and a read out state is enabled for the memory cell transistor that corresponds to address signal AD. As a result, Y selector
17
inputs the data stored in this selected memory cell transistor via the main bit line, and outputs the data to sense amplifier circuit
9
as a data signal DG.
At this time, the memory cell transistor performs data storage by changing the threshold voltage, which is under ON/OFF control. In other words, when the threshold voltage is changed so that the word selection line that is connected to the gate is activated and the memory cell transistor enters the ON state, data is stored by means of the flow of current proportionate to this threshold value. In the case of binary information, two thresholds, i.e., a state in which current flows easily and a state in which current does not flow easily, are controlled.
Sense amplifier circuit
9
compares the current of this input data signal DG and the current of a reference signal RG that is input from reference circuit
10
. If the current of data signal DG is smaller than the current of reference signal RG at this time for example, then the current state is one in which the threshold value is high and current does not readily flow. Therefore, the data stored in the memory cell transistor is [H]. Conversely, if the current of the data signal DG is larger than the current of the reference signal RG, then the data stored in the memory cell transistor is [L].
Next, sense amplifier circuit
9
outputs the results of this comparison of the currents as data signal D
0
.
Reference circuit
10
is formed of a constant voltage circuit (a voltage stabilizer) that outputs a voltage level which is intermediate between the voltage level of the bit signal when the data stored in the memory cell transistor in memory cell area
16
B is [H], and the voltage level of the bit signal when the data stored in the memory cell transistor in memory cell area
16
B is [L].
In addition, for example, reference circuit
10
may also have a design in which a reference transistor is employed that is controlled by a threshold value where the voltage level of reference signal RG, which is selected by the word selection line and determined by the current flow, assumes a voltage level that is intermediate between the bit signal voltage level when the data stored in the memory cell transistor is [H] and the bit signal voltage level when the data stored in the memory cell transistor is [L].
Precharge circuit
8
prevents the flow of current to memory cell transistors other than the one selected, by means of impressing a bias voltage onto the main bit lines that are connected to the non-selected memory cell transistors that are adjacent to the memory cell transistor within memory cell area
16
B that was selected by the address signal AD.
The bias voltage supplied from precharge circuit
8
at this time is output as precharge signal PC to the main bit line that was selected by Y selector
17
in accordance with address signal AD.
Bank decoder
13
decodes a portion of address signal AD, and outputs bank selection signal BS
0
~bank selection signal BS
3
as the decoded results to the bank selection signal lines corresponding respectively to bank selector
16
A and bank selector
16
C. Bank selection signal BS
0
and bank selec
NEC Corporation
Scully Scott Murphy & Presser
Tran Andrew Q.
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