Method of fabricating conductive line structure

Details Method of fabricating conductive line structure Method of fabricating conductive line structure

1999-06-19

2001-08-14

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257S386000

Reexamination Certificate

active

06274477

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabrication method. More particularly, the present invention relates to a method of fabricating a conductive line structure.
2. Description of the Related Art
As linewidth of a semiconductor device reduces, distance between conductive layers is accordingly reduced. This, in turn, causes a parasitic capacitor effect to become serious. The dielectric constant of an inter-metal dielectric (IMD) layer between the conductive layers is an important factor in the prevention of the parasitic capacitor effect. As the dielectric constant increases, the parasitic capacitor effect occurs more easily. Thus, a resistance-capacitance time delay (RC delay) is increased. The increase in the RC delay may further decrease the operation speed of devices. Therefore, it is necessary to lower the dielectric constant of a dielectric layer, so as to decrease the RC delay and increase the operation speed.
Reference is made to
FIG. 1
, which shows a conventional conductive line structure. A first dielectric layer
102
is formed on a substrate
100
. A conductive line
104
is formed on the first dielectric layer
102
. A second dielectric layer
106
is formed over the substrate
100
.
Because the conductive layer
104
is conductive and the dielectric material is formed between neighboring conductive lines
104
, it easily induces a parasitic effect. In addition, as the distance between neighboring conductive lines
104
decreases, the parasitic capacitance increases. Thus, the RC delay becomes serious.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a conductive line structure. A first dielectric layer is formed on a substrate. A patterned conductive layer is formed on the first dielectric layer. The patterned conductive layer comprises an opening. The opening exposes a portion of the first dielectric layer. A conformal stop layer is formed over the substrate. The conformal stop layer is conformal to the conductive layer. An oxide layer is formed in the opening but does not completely fill the opening. A portion of a sidewall of the opening is exposed. A spacer is formed on the exposed sidewall of the opening. The oxide layer is removed. A second dielectric layer is formed over the substrate to fill the opening. A void is formed in the second dielectric layer in the opening.
The void is full of air, whose dielectric constant is low. Thus, because of the formation of the void, the dielectric constant in the opening is decreased. The parasitic effect is reduced and RC delay is decreased, as well.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5641712 (1997-06-01), Grivna et al.
patent: 5750415 (1998-05-01), Gnade et al.
patent: 6035530 (1999-05-01), Hong

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