One-time programmable logic cell

Details One-time programmable logic cell One-time programmable logic cell

2000-07-28

2001-03-20

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having fuse element

C327S525000

Reexamination Certificate

active

06205077

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a fuse in CMOS technology, and more specifically to a one-time programmable (OTP) cell for providing a logic state according to the state of the fuse.
BACKGROUND OF INVENTION
FIG. 1
shows a conventional example of an OTP cell. It includes a fuse
10
connected between a programming terminal
12
and a node A. Node A is connected to high supply voltage Vdd by a current source
14
. The input of an inverter
16
is connected to node A, and output S of this inverter provides a logic state corresponding to the state of fuse
10
.
Further, node A is connected to low supply voltage Vss by a reset transistor MN
1
.
In normal operation, programming terminal
12
is connected to low supply voltage Vss. Upon circuit power-on, reset transistor MN
1
receives a reset pulse INIT on its gate. Transistor MN
1
is thus turned on for a short time to bring the voltage of node A to voltage Vss. After the reset pulse, transistor MN
1
is off. If fuse
10
is conductive, it maintains node A to voltage Vss and inverter
16
provides logic state 1. If fuse
10
is off, current source
14
draws node A to voltage Vdd and inverter
16
then provides logic state 0.
Fuse
10
is often formed of the oxide layer separating the substrate from the gate of a MOS transistor. A P-channel MOS transistor having an interconnected drain, well and source is generally used. Thus, the unprogrammed fuse is isolating. To program the fuse, the oxide layer is broken down, to then become conductive. For this purpose, a programming voltage Vpp much greater than supply voltage Vdd is applied between the two surfaces of the oxide layer. In the cell of
FIG. 1
, voltage Vpp is applied on programming terminal
12
while transistor MN
1
is turned on.
Programming terminal
12
is generally external to the circuit, since voltage Vpp would risk damaging the circuit components if it were transmitted internally. The short-circuit of node A to voltage Vss through transistor MN
1
prevents a possible increase of the voltage on node A under the effect of programming voltage Vpp.
A disadvantage of the cell of
FIG. 1
is that a current source
14
that permanently provides current when the corresponding fuse
10
is conductive is required for each fuse
10
. This discourages the use of OTP cells in applications where a small consumption is desired.
SUMMARY OF INVENTION
The disclosed embodiments of the present invention provide an OTP cell having a negligible current consumption. To achieve this, the embodiments of present invention provide a one-time programmable cell including an inverter providing a logic state according to the state of the cell; a fuse coupled between a first supply voltage and the inverter input; and a current source coupled between the fuse and the second supply voltage. The inverter is supplied from the second supply voltage through a first diode-connected transistor and the current source is formed of a second transistor controlled by the inverter output, this second transistor having a threshold voltage greater than that of the first transistor. According to an embodiment of the present invention, the first and second transistors are P-channel MOS transistors, the second supply voltage being a high voltage. According to an embodiment of the present invention, the channel length of the second transistor is greater than that of the first transistor. According to an embodiment of the present invention, the cell includes a reset transistor connecting the connection node between the fuse and the second transistor to the first supply voltage. The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.


REFERENCES:
patent: 4486671 (1984-12-01), Ong
patent: 4621346 (1986-11-01), McAdams
patent: 5173616 (1992-12-01), Hinooka
patent: 5457656 (1995-10-01), Fu
patent: 5566107 (1996-10-01), Gilliam
patent: 5838625 (1998-11-01), Cutter et al.
patent: 0 480 475 (1992-04-01), None
patent: 60-249423 (1985-12-01), None

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