File memory device using flash memories, and an information...

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring

Reexamination Certificate

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C711S005000, C711S103000

Reexamination Certificate

active

06272610

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
The present application is relevant to U.S. Pat. No. 5,530,828 in the names of Kenichi Kaki et al., and of which priority is based on Japanese Patent Application Serial No. 4-163074 filed on June 22, 1992, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an information processing apparatus incorporating a file memory device, and particularly to a file memory device suitable for the speed-up of file access and to an information processing apparatus using it.
2. Description of the Related Art
The file memory is an almost indispensable peripheral device for general-purpose information processing systems such as personal computers. Generally, file memories are built into the main unit of the information processing system, thereby allowing the user to deal with capacious files.
Recently, notebook and palm-type personal computers have gained popularity, their appeal lying principally on their usefulness in terms of portability. Accordingly, file-memory-based semiconductor memory chips have been used in place of magnetic-type disk memory because the latter is not ideally suited to a notebook computer environment, i.e. They are not reliable against vibrations and consume too much power. An example of a system which employs a semiconductor file memory based on a flash memory is disclosed in Japanese patent publication JP-A-2-292798.
A flash memory is an electrically erasable and programmable non-volatile memory. Because they can be manufactured at comparatively low cost in large-scale production, flash memories have proven to be one of the most effective storage mediums for use as a semiconductor file memory. The technique of the above-mentioned patent publication is intended to solve many of the problems that are encountered in designing a file memory based on the flash memory. Specifically, the cited patent publication recognizes that frequent erasing operations in a file memory causes damage to many of its file memory elements. The cited patent proposes a method of alleviating this drawback of the file memory, and in addition proposes a method of speeding up erasing operations required for rewriting data therein. The semiconductor file memory further achieves compatibility with the magnetic disk memory with respect to the way in which it interfaces with main information processing apparatus; with the principal intention of reorganizing information processing systems by replacing their magnetic disk memories with semiconductor memories.
The above-mentioned prior art semiconductor file memory achieves compatibility with magnetic disk memories by using the existing interface bus of the main information processing apparatus. Although this design principle allows the user to easily accept the semiconductor memory, because of its compatibility with the magnetic disk memory, it does not take advantage of the superiority which the semiconductor memory has over magnetic disk memories. For example, a semiconductor memory in the form of a static storage medium enables very fast data access. The magnetic disk memory, in contrast, reads or writes data at certain positions on a turning disk. This fast access property of the semiconductor memory, however, cannot be utilized with the interface that is designed for the magnetic disk memory.
Magnetic disk memories used in presently existing information processing apparatuses such as personal computers are slow in data access relative to the main memory access. Therefore, the magnetic disk memory does not need to operate in synchronism with the CPU of processing apparatus, and it transacts data over an asynchronous data bus. In contrast, semiconductor memories are fast enough to operate in synchronism the CPU. The ability of a file memory to operate synchronously with a CPU becomes significant.
However, if it is intended to overcome the difference of the data bus width of a flash memory chip from the CPU data bus width by using memory chips in parallel, a new problem arises. Namely, a flash memory has a fixed size of unit erasure block area, which is typically 512 bytes. Accordingly, when multiple memory chips are used in parallel, an area equal to the unit block area (e.g., 512 bytes) multiplied by the number of chips in parallel in erased at once.
Many personal computers have a unit storage data block for file management (i.e., a sector having a size) of 512 bytes. Thus, for example, if it is intended to use four flash memory chips in parallel, a rewrite access to one file sector will result in the erasure of an area that is four times the sector. This unit erasure block size is too large, and unintentional erasure of other data can occur.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a semiconductor file memory device that can access file data faster than prior art semiconductor file memory devices, and which is inexpensive when used in an information processing apparatus.
It is another object of the present invention to provide a method controlling the semiconductor file memory device, as mentioned above.
Another object of the present invention is to provide a semiconductor file memory device of the aforementioned type that is based on a flash memory having a relatively large unit erasure block size which does not affect file data located in other portions of the memory, and to provide a method for controlling such a memory device.
A further object of this invention is to provide a semiconductor file memory device which is compact in size.
A further object of this invention is to provide a file memory device that effectively uses fragmentary memory areas, which are created during the process of storing multiple files of various sizes by varying the file storage method dynamically.
The semiconductor file memory device of the present invention uses a parallel arrangement of memory element groups which has, one, a unit erasure block size greater than the data bus width of the file memory device and, two, a data access width smaller than the data bus width of the file memory device. The file memory, which operates to store file data through the data bus, comprises: a file division means for dividing file data, that includes one or more unit storage data blocks into combined blocks which include a combination of arbitrary unit storage data blocks; a data distribution means for combining arbitrarily data from the data bus into a unit data size equal to a predetermined data access width, and for making the combined data correspond to an arbitrary combination of memory element groups equal in number to the unit size data; and a control means for controlling the data distribution means so that each combined block is stored in a corresponding one of the arbitrary combinations of memory element groups.
The information processing system of the present invention is equipped with a built-in semiconductor file memory device in the form of a storage medium, such as a flash memory, having a large unit erasure block size, which memory can therefore realize a level of fast file access performance that is superior compared to magnetic disk-type memories. Advantageously, the CPU operation of the information processing system of the present invention can be timed to operate synchronously with the file memory device by manipulating a Ready signal to be input into the CPU so that it is halted properly. Also, in this system fast file access is possible even if a flash memory chip has a number of access data bits different from the system data bus width.
The file memory device of the present invention advantageously can be used to provide continuous sector access in reading or writing a capacious file in which the file access time is crucial for the user.
In addition, the file memory device has a flexible system design in terms of both system data bus width and the number of access data bits of flash memory chips that vary depending on system application, performance, and technical trends of time. The invention

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