Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
1997-08-20
2001-04-24
Yoo, Do Hyun (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S171000, C711S218000, C710S120000, C710S120000, C710S120000, C710S035000, C710S029000
Reexamination Certificate
active
06223266
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to a system and method for interfacing systems within a computer system and in particular to a system and method for interfacing an input/output system to a host computer over a high speed computer bus.
Computer systems, and in particular, central processing units (CPUs) in the computer system require a certain amount of memory to store software application code, operating system code as well as data. During the operation of a typical computer system, the CPU executes the application code stored in the memory and stores and/or retrieves data from the memory. In addition to the memory, the CPU may also require additional hardware circuitry and memory to interface with different electrical computer buses which may have different purposes and different bus standards. These computer buses may connect input/output (I/O) systems and devices to the CPU, for example.
Some of these input/output devices may have a microprocessor or microcontroller located in the input/output device to process data being communicated to the input/output device to improve the speed or functionality of the I/O operations. Other devices may not, so the CPU in the computer system may have to process all of the input/output devices instructions and data as well as its own instructions and data. This can degrade the speed of the CPU. The performance of the input/output device is also slow because the instructions and data from the input/output device at times may have a lower priority than the CPU's own data and instructions. Some typical input/output devices may have some intelligence, such as a microcontroller or microprocessor so that instructions of the device can be executed, and data can be processed by the microprocessor located within the input/output device. Therefore, the speed of processing the instructions and data of the input/output device is not dependent on the speed of the CPU in the computer system. These input/output devices normally require a local memory for storing the software application code being executed by the microprocessor in the input/output device and the data operated on by the microprocessor. The additional memory in the input/output device increases its cost and increases its overall physical size requirements. It is often desirable that data transfers occur between the local memories for the input/output device and the main memory of the computer system.
Many system buses and memory devices are capable of high speed data transfers, such as block transfers, in which a block of sequential memory addresses is transferred. These high speed transfers are known as “burst” transfers since a sequential block of data may be rapidly transferred (e.g., bursted) to another memory location or another memory connected to the same computer bus. These burst transfers are very efficient for general bus operations (e.g., the transfer of commands and data from different units within a computer system), but cannot adequately serve a microprocessor executing software code because the software code is typically accessed from non-sequential memory locations within the memory and thus requires non-sequential accessing of the memory which is not compatible with the sequential memory address burst transfers over computer buses. The burst transfer of sequential memory addresses also does not adequately serve any other type of retrieval or processing of non-sequential data.
None of the known systems provides a general purpose, processor unspecific memory architecture which can take advantage of the high speed sequential data transfers possible with a computer bus while also serving as the main memory for a microprocessor in an input/output device which requires randomly accessible data. It is desirable to provide a memory architecture and system that can take advantage of high speed burst transfers over a high speed computer bus for input/output devices that require randomly accessible data.
Thus, there is a need for a system and method for improved, more efficient communication of data between an input/output device and a computer system over a high speed computer bus which avoids the foregoing and other problems of known systems and methods, and it is to this end that the present invention is directed.
SUMMARY OF THE INVENTION
In accordance with the invention, a system and method for interfacing an input/output system to a computer system having a local bus that connects to a microprocessor is provided in which the computer system and input/output system are connected by a high speed system bus. The interface system may interface the high speed system bus to a memory within the interface system and also interface the interface system to the local bus of the input/output system. Because the memory within the interface system is connected directly to the high speed system bus, the memory may communicate with the main memory of the computer system over the high speed computer bus to transfer burst ordered blocks of data into and out of the memory located within the interface system at high speed. The memory of the interface system may also act as the main memory for the processor in the input/output system and permit random access of data by the processor. More specifically, the interface system may include the bus interfaces, a cache memory, a cache controller, debugging aids and a shared memory. The coupled memory device may also be incorporated into a single semiconductor component or integrated circuit.
The invention may also provide a system for interfacing between a plurality of microprocessors connected to a high speed bus in which an interface device with a memory is connected to each microprocessor and each of the interface devices are in turn connected to the high speed system bus of the computer system. For each microprocessor, the memory in the interface device is connected to the high speed system bus and may communicate sequential or other burst ordered blocks of data with the computer system or with the other microprocessors over the high speed computer bus. The memory in the interface device may also act as a main memory for the microprocessor since the cache memory may permit the microprocessor to randomly access data in the memory.
The invention also provides a method for filling and updating a cache memory, such as in the coupled memory device, in which a least recently used age list of memory pages indicates that a memory page in the cache is older (i.e., not recently used) or newer (i.e., more recently used). Any missing cache lines in newer pages may be filled while any modified cache lines in older pages may be written back to main memory. In this method, the newest pages are always ready to be accessed while the oldest pages may be reused as needed.
The system and method may also provide a system for locking certain memory pages of the cache memory than contain time critical data for the processor so that these locked memory pages cannot be re-used until those memory pages are unlocked or unnailed. The system and method may also provide a system for removing certain memory pages from the cache memory regardless of their position in the least recently used stack so that these memory pages are re-used immediately once any modified cache lines have been written back into the main memory. In addition, a unique system and method for reading the requested data from the main memory is provided in which, during a first request, the actual requested data is read from the main memory directly to the I/O processor, and during a second request, an entire cache line of data including the requested data is loaded into the cache memory. Thus, the processor obtains the requested data as fast as possible and the accuracy of the data in the cache memory is maintained. A unique system and method for writing modified instruction data into the instruction cache is also provided in which the I/O processor may write modified instruction data to the cache memory, but the cache memory controller actually writes the modified cache line imm
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
McLean Kimberly
Yoo Do Hyun
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