Method of fabricating metal interconnect

Details Method of fabricating metal interconnect Method of fabricating metal interconnect

1999-07-09

2001-03-27

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S623000, C438S624000, C438S639000, C438S699000, C438S700000, C438S970000

Reexamination Certificate

active

06207556

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for fabricating multi-level interconnects for a semiconductor device. More particularly, the present invention relates to a fabrication method for a via.
2. Description of Related Art
In the integrated circuit (IC) process, devices are connected through formation of metal interconnects. Because of an ever-increasing IC integration and more complex function, the metal interconnects are connected to the devices on each circuit with a multi-level metal layer.
In the metal interconnect, the top and bottom metal layers are connected through a via. During the early multi-metallization process, the metal layer only contains a few levels, while the line width in the process is much wider. Thus, the part of the metal layer which contacts with the via has a border, so that the via is formed and located completely above the surface of the metal layer. This via is known as a landed via.
However, as the design rules for the device become more detailed, the integration is increased by having borderless parts which contact with the via in the metal layer. It will therefore be more difficult to manufacture the via without a border. Once a misalignment occurs in the photolithographic process, the via is no longer located completely above the surface of the metal layer, producing what is known as an unlanded via.
FIG. 1A
is a schematic diagram illustrating a metal interconnect in the prior art. Referring to
FIG. 1A
, the manufacture of the via involves covering a substrate
100
having metal lines
102
formed thereon with an oxide layer
104
. A patterned photoresist layer (not shown) is formed on the oxide layer
104
. With the photoresist layer serving as an etching mask, the oxide layer
104
is etched to form a via opening
106
in the oxide layer
104
. The photoresist layer is then removed. A titanium (Ti)/Ti
x
N
y
barrier layer
108
and a tungsten (W) layer
110
are formed in the via opening to complete the manufacture of the via.
Typically, when the via is manufactured with the above method, an over-etching step is performed to etch the oxide layer
104
, which overcomes the loading effect of etching. But, once a misalignment has occurred in the process, a cavity
112
is likely to form as shown in
FIG. 1B
, along the sidewall of the metal line
102
due to the over-etching of the oxide layer
104
, so that the via opening
106
loses its preformed profile.
However, this narrow cavity
112
causes problems for the subsequent metallization process. For example, after depositing a Ti layer
107
into the via opening
106
and the cavity
112
, the subsequent Ti
x
N
y
layer
109
in the cavity
112
produces an overhang
114
due to the excessive narrowness of the cavity
112
. Therefore, the Ti layer
107
not covered by the Ti
x
N
y
layer
109
is exposed. As the W
x
F
y
is adopted as a gas source for the subsequent W layer
110
, the F ions react with the exposed Ti layer
107
to produce TiF
3
and other compounds in the process for depositing the W layer
110
. TiF
3
is a volatile compound, which produces a phenomenon similar to a volcano eruption in the subsequent thermal process, thus forming a volcano opening in the via. This leads to a rise in the via resistance and a decrease in the device reliability. Consequently, the process window becomes very narrow when manufacturing the interconnect with conventional method.
To increase the performance efficiency of the device and reduce resistance-capacitance (RC) time delay, it has become a new trend for the semiconductor process development to employ a dielectric material having low dielectric constant as an inter-metal dielectric (IMD) layer. However, in the fabricating process for the via with the above method, once a misalignment occurs, the cavity
112
produced by over-etching exposes the dielectric material having a low dielectric constant. As the dielectric material having a low dielectric constant is generally water absorbent, water vapors are produced during the thermal metallization process. The thermal metallization process fills the via opening
106
with a metal layer
110
after water is absorbed in the previous processes, which involve removing the photoresist and washing. As a result, it is difficult to fill the via opening
106
with the metal layer
110
, causing a poor step coverage of the metal layer
110
in the via opening
106
. This further leads to a formation of keyhole and occurrence of metal poison effect.
SUMMARY OF THE INVENTION
The invention provides a fabrication method for a metal interconnect, which method involves forming a first dielectric layer on a substrate with metal lines formed thereon, wherein the top surface of the dielectric layer is lower than the surfaces of the metal lines. As a result, the top surface and a part of the sidewall of the metal line are exposed. A spacer is formed on the exposed sidewall of the metal line, followed by forming a second dielectric layer on the substrate. With the spacer serving as an etch stop, a via opening is formed in the second dielectric layer. The via opening is then filled with a metal layer to form a via plug.
As embodied and broadly described herein, the spacer mentioned above has a different etching ratio from the second dielectric layer, while the width of the spacer is approximately greater than the process margin. Hence, in the process for forming the via opening, the spacer can serve as the etch stop when etching the second dielectric layer even if a misalignment occurs. Thus, the via opening is located completely above the metal line and the spacer, and there is no etching on the first dielectric layer which might otherwise expose the first dielectric layer by the via opening.
According to the present invention, a spacer is formed on the sidewall of the metal line to form an etching dielectric layer which is an etching stop layer for the via opening. In the present invention, the profile of the via opening can be controlled, while the process window and the process reliability are increased. This prevents cavity formation due to the misalignment and the loading effect. Furthermore, this prevents the formation of a volcano opening and associated electrical problems, as it is difficult to fill the cavity located along the sidewall of the metal line with a barrier layer during the process for fabricating the via plug.
In addition, the dielectric material having a low dielectric constant also acts as a first dielectric layer in order to reduce the RC time delay and to increase the execution efficiency. According to the present invention, the first dielectric layer is not exposed even when a misalignment occurs. Therefore, the via poisoning effect by water absorption of the first dielectric layer after exposing the dielectric material having a low dielectric constant is not an important issue even though the first dielectric layer of the present invention is the same dielectric material having a low dielectric constant.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5286674 (1994-02-01), Roth et al.
patent: 5399533 (1995-03-01), Pramanik et al.
patent: 5482900 (1996-01-01), Yang
patent: 5925932 (1999-07-01), Tran et al.

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