Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1999-08-13
2001-08-21
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C326S039000, C326S113000
Reexamination Certificate
active
06278290
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to programmable logic devices, and more particularly to programmable logic devices incorporating low threshold voltage (low V
th
) transistors.
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) typically include a plurality of logic elements and associated interconnect resources that are programmed by a user to implement user-defined logic operations (that is, a user's circuit). PLDs are programmed using a personal computer or workstation, appropriate software and in some cases a device programmer. Therefore, unlike application specific integrated circuits (ASICs) that require a protracted layout process and an expensive fabrication process to implement a user's logic operation, a PLD may be utilized to implement the logic operation in a relatively quick and inexpensive manner.
FIG.
1
(A) is a simplified diagram showing a basic Field Programmable Gate Array (FPGA)
100
, which is a type of PLD. FPGA
100
includes an array of configurable logic blocks (CLBs) CLB-
1
,
1
through CLB-
4
,
4
that are surrounded by input/output blocks (IOBs) IOB-
1
through IOB-
16
, and programmable interconnect resources that include vertical interconnect wiring segments
120
and horizontal interconnect wiring segments
121
extending between the rows and columns of CLBs and IOBS. Each CLB includes configurable combinational circuitry and optional output registers that are programmed to implement a portion of a user's logic function. The interconnect wiring segments of the programmable interconnect resources are configured using various switches to generate signal paths between the CLBs that link the logic function portions. Each IOB is similarly configured to selectively utilize an associated pin (not shown) of FPGA
100
either as a device input pin, a device output pin, or a bi-directional pin. Although greatly simplified, FPGA
100
is generally consistent with FPGAs that are produced, for example, by Xilinx, Inc. of San Jose, Calif.
FIGS.
1
(B) through
1
(D) are simplified diagrams showing examples of the various switches associated with the programmable interconnect resources of FPGA
100
. FIG.
1
(B) shows an example of a six-way segment-to-segment switch
122
that selectively connects vertical wiring segments
120
(
1
) and
120
(
2
) and horizontal wiring segments
121
(
1
) and
121
(
2
) in accordance with configuration data stored in memory cells M
1
through M
6
. Alternatively, if horizontal and vertical wiring segments
120
and
121
do not break at an intersection, a single transistor makes the connection. FIG.
1
(C) shows an example of a segment-to-CLB/IOB input switch
123
that selectively connects an input wire
110
(
1
) of a CLB (or IOB) to one or more interconnect wiring segments in accordance with configuration data stored in memory cells M
7
and M
8
. FIG.
1
(D) shows an example of a CLB/IOB-to-segment output switch
124
that selectively connects an output wire
115
(
1
) of a CLB (or IOB) to one or more interconnect wiring segments in accordance with configuration data stored in memory cells M
9
through M
11
.
Signal Contention Problem
FIG.
2
(A) is a simplified schematic showing one row of CLBs of FPGA
100
(see FIG.
1
(A)). As indicated in FIG.
2
(A), CLB-
1
,
1
is programmably connected to wiring segment
121
(
1
) via CLB-to-segment output switch
124
(
1
), and CLB-
1
,
2
is programmably connected to wiring segment
121
(
2
) via CLB-to-segment output switch
124
(
2
). Wiring segments
121
(
1
) and
121
(
2
) are programmably connected via segment-to-segment switch
122
(
1
).
When power is initially applied to a typical PLD (referred to below as “power-up”), the configuration memory cells of the PLD “wake up” in random states. These random states sometimes cause the configurable logic circuits (e.g., IOBs and CLBs) to transmit opposing (i.e., high and low voltage) signals onto the wiring segments of the interconnect resources. A signal contention problem occurs when the sources of these opposing signals are linked through the interconnect resources, thereby potentially damaging and/or locking-up the PLD.
FIG.
2
(B) shows a relevant portion of the CLB row of FIG.
2
(A), and illustrates an example of a power-up signal contention problem between CLB-
1
,
1
and CLB-
1
,
2
(see FIG.
2
(A)). The present example assumes that the internal circuitry of CLB-
1
,
1
“wakes up” in a state that transmits a high (VDD) output signal to CLB-to-segment output switch
124
(
1
). Conversely, the internal circuitry of CLB-
1
,
2
“wakes up” in a state that transmits a low (GND) output signal to CLB-to-segment output switch
124
(
2
). In addition, the present example assumes that memory cells M
11
of CLB-to-segment output switches
124
(
1
) and
124
(
2
) “wake up” to pass these high and low signals to wiring segments
121
(
1
) and
121
(
2
), respectively. Finally, the present example assumes that memory cell M
6
of segment-to-segment switch
122
(
1
) “wakes up” in a state that turns on its associated pass transistor to connect wiring segments
121
(
1
) and
121
(
2
). Based on the “wake up” states provided above, signal contention is generated between VDD CLB-
1
,
1
and GND CLB-
1
,
2
that can potentially damage and/or create unacceptably high current in FPGA
100
.
Signal contention can also occur after device power-up in PLDs that support reconfiguration. Reconfiguration typically includes deactivation of the PLD (which operates according to “old” configuration data), writing “new” reconfiguration data into the configuration memory, and then re-activating the PLD such that it operates according to the “new” configuration data. Signal contention can occur during this reconfiguration process while the “new” configuration data is being written into the configuration memory. Specifically, signal contention can occur while the configuration memory contains some “old” configuration data and some “new” configuration data (i.e., while the new configuration data is being written into configuration memory). For example, referring to FIG.
2
(B), assume the “old” configuration data causes CLB-
1
,
1
to transmit a high (VDD) output signal to CLB-to-segment output switch
124
(
1
), causes CLB-to-segment output switch
124
(
1
) to pass this high signal to wiring segment
121
(
1
), and causes segment-to-segment switch
122
(
1
) to connect wiring segments
121
(
1
) and
121
(
2
). If this “old” configuration data is still stored in the configuration memory when “new” configuration data is written that causes CLB-to-segment output switch
124
(
2
) to transmit a low (GND) output signal from CLB-
1
,
2
to interconnect wiring segment
121
(
2
), then signal contention is generated between VDD CLB-
1
,
1
and GND CLB-
1
,
2
that can potentially damage and/or create unacceptably high current in FPGA
100
.
A well-known mechanism for preventing signal contention at device power-up is to fabricate a PLD using asymmetric transistors that are biased to “wake up” in a known state. However, such asymmetric transistors are unreliable, and also require significantly more area than symmetric transistors.
Crowbar Current Problem
FIG.
2
(C) is a simplified schematic showing another portion of FPGA
100
of FIG.
1
(A), and illustrates an example of how buffers utilized in the interconnect resources of some PLDs can create a significant crowbar current problem. FIG.
2
(C) shows a portion of the interconnect resources of FPGA
100
including interconnect wiring segments
121
(
3
) and
121
(
4
) that are programmably connected by a pass transistor
210
of segment-to-segment switch
122
(
2
), and a buffer circuit
220
that is connected between interconnect wiring segment
121
(
4
) and an input terminal of CLB-X,Y. Buffer circuit
220
includes a CMOS inverter
225
having a P-channel transistor P
1
and an N-channel transistor N
1
, each having a gate terminal connected to interconnect wiring segment
121
(
4
). During operation of FPGA
100
, logic signals (e.g., VDD or ground) are tran
Bever Patrick T.
Paik Steven S.
Tokar Michael
Xilinx , Inc.
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