Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-05-21
2001-01-23
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S238000
Reexamination Certificate
active
06177300
ABSTRACT:
BACKGROUND OF THE INVENTION
The present embodiments relate to transistor circuits, and are more particularly directed to a memory with storage cells having silicon-on-insulator (“SOI”) drive and access transistors with tied floating body connections.
The technology of many modem circuit applications continues to advance at a rapid pace, with one incredibly prolific type of circuit, and one which is highly developed, being digital memory. For such memories, consideration is given to all aspects of design, including maximizing efficiency and increasing performance. These considerations may be further evaluated based on the integrated circuit device in which the memory is formed, where such circuits may be implemented either as stand-alone products, or as part of a larger circuit such as a microprocessor. One often critical factor with respect to digital memories is the cost of the device and this cost is often affected by the overall size of the memory architecture. Another factor with respect to digital memories includes noise immunity. Thus, a desirable memory reduces device size and provides an acceptable immunity to noise signals.
In the current art, memory size may be affected by various factors. In one prior art approach as detailed later, memory size is affected by connections used for each of the drive and access transistors in each of the memory cells of the configuration. Specifically, it is known in the memory art for each memory cell to often include at least two access transistors, where access is through those transistors to corresponding storage nodes of the cell. It is further known to often include at least two drive transistors, where those transistors provide the ability to drive an output node through an access transistor, according to the state of the memory cell. In both cases, under current memory architectures these two types of transistors are sometimes formed using silicon-on-insulator (SOI) technology. In this instance, it is common to tie the body of each of the access and drive transistors to a fixed and relatively low potential. For example, often the bodies of the access transistors are tied to ground, while often the bodies of the drive transistors are tied to the source of the drive transistors, where the source itself is connected to ground. These connections are performed in the prior art so that the body of each transistor is fixed to a known potential, rather than permitting the body potential to fluctuate which could otherwise occur due to the tendency of the body potential to deviate due to the signal conditions experienced by the transistor. While these body-to-ground connections therefore provide acceptable operational performance, they also provide a drawback in that they require an additional connection per transistor and, thus, consume additional area on the integrated circuit in which the memory configuration is formed.
The above considerations and drawbacks are presented in more detailed fashion below. Based on that presentation, one skilled in the art will appreciate that there is a need to address these drawbacks. The preferred embodiments described below do indeed address these drawbacks, and thereby provide a more efficient and desirable integrated circuit configuration.
BRIEF SUMMARY OF THE INVENTION
In one preferred embodiment, there is an integrated circuit. The integrated circuit comprises a first SOI transistor having a body and for performing first function. The integrated circuit further comprises a second SOI transistor having a body and for performing a second function different than the first function. Lastly, the integrated circuit comprises a conductor connecting the body of the first SOI transistor to the body of the second SOI transistor such that the bodies of the first SOI transistor and the second SOI transistor float together.
In another embodiment, there is an integrated circuit memory array, wherein the memory array further comprises a first bitline and a plurality of memory storage cells. Each of the plurality of memory cells further comprises a first SOI access transistor and a first SOI drive transistor, where each of these transistors comprises a plurality of nodes, the plurality of nodes comprising a first source/drain, a second source/drain, a gate for receiving a potential to enable a conductive path between the first source/drain and the second source/drain, and a body terminal coupled to a body region disposed between the first source/drain and the second source/drain. For each of the memory cells, the first source/drain of the first SOI access transistor is coupled to the first bitline, and the first source/drain of the first SOI drive transistor is coupled to the second source/drain of the first SOI access transistor. Also for each of the cells, there is further included a body connection coupling the body of the first SOI access transistor to the body of the first SOI drive transistor such that the bodies of the first SOI access transistor and the first SOI drive transistor are connected to float together. Other circuits, systems, and methods are also disclosed and claimed.
REFERENCES:
patent: 6087893 (2000-07-01), Oowaki et al.
J.A. Mandelman, F. Assaderaghi, and L.L. Hsu; “SOI MOSFET Mismatch Due to Floating-Body Effects”, pp. 164-165 of 1997 IEEE International SOI Conference Proceedings, dated Oct. 6-9, 1997.
Bosshart Patrick W.
Houston Theodore W.
Brady III Wade James
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tsai H. Jey
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