Dynamic logic circuits using selected transistors connected...

Details Dynamic logic circuits using selected transistors connected... Dynamic logic circuits using selected transistors connected...

1999-09-24

2001-06-12

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000, C326S121000

Reexamination Certificate

active

06246266

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to transistor circuit configurations and are more particularly directed to dynamic logic circuits.
In many modern circuit applications, it is desirable to increase the operational speed of the circuit application. For example, in microprocessor design the circuits which make up speed-limiting portions or affect the speed of the microprocessor are constantly scrutinized and re-designed to increase the overall microprocessor speed. Increased speed increases performance and, therefore, permits more detailed and sophisticated processing capabilities in a shorter amount of time.
To increase the speed of microprocessors, as well as other circuits where speed is important, dynamic logic transistor circuits are currently used because they often provide increased speed as compared to static logic transistor circuits. A dynamic logic circuit is characterized by operating in two phases. First, a precharge node is set to a first potential during a precharge phase. Second, during an evaluate phase, if a logic condition represented by the circuit is satisfied, the precharged node is discharged, thereby changing the logic output of the circuit. In other words, at the conclusion of the precharge phase, the precharged node causes a first logic state to be output by the dynamic logic circuit and if the precharged node is discharged during the evaluate phase, the output of the dynamic logic gate represents a second logic state differing from the first logic state. The act of discharging to change states, when accomplished using one or more n-channel transistors to gate the transition from precharge to discharge, represents a speed increase over the prior operation of static circuits which in one instance accomplished a transition with a network of n-channel transistors while in another instance accomplished the opposite transition with a network of p-channel transistors.
Another performance technique currently in use in manufacturing is to target the threshold voltage of transistors given certain circuit expectations. Particularly, typically a manufacturer will build transistors, or make available transistor fabrication processes, which include transistors of a given threshold voltage. When providing this process, the manufacturer typically considers the tradeoff in speed improvement versus power consumption. To increase operational speed, it is known that the threshold voltage of all of the transistors within a circuit may be reduced. By reducing the threshold voltage, the drive current of these transistors is increased. However, the leakage current of those same transistors is also increased. Indeed, note that this approach becomes even more limiting as power supply voltages are reduced and the threshold voltage of the transistor becomes a greater percentage of the power supply voltage. Consequently, one approach is to lower the threshold voltage of the transistor but this increases current leakage and therefore also increases overall standby power consumption. Thus, often a manufacturer anticipates a certain level of leakage to be the acceptable limit, and in view of that limit, adjusts known parameters so that each of the transistors of the circuit share a designated threshold voltage which will provide that limit.
While the above approaches are representative of the art for advancing circuit operational speed, they provide various limitations or drawbacks. For example, the dynamic logic speed is still limited by the threshold voltage of the transistors used in the logic. As another example, an advance in speed by reducing threshold voltage typically increases standby power consumption caused by leakage current. The inventor of the present embodiments has recognized the above considerations and has provided various improvements in certain U.S. patents, where in those patents dynamic logic circuits are constructed using a combination of low threshold voltage transistors and high threshold voltage transistors. For example, U.S. Pat. No. 5,831,451, entitled “Dynamic logic circuits using transistors having differing threshold voltages,” issued Nov. 3, 1998, and is hereby incorporated herein by reference. In U.S. Pat. No. 5,831,451, there is described a dynamic logic system whereby each discharge path in the system includes at least one high threshold voltage transistor for reducing current leakage during the precharge phase, and where preferably each such discharge path further includes one or more low threshold voltage transistors to increase the speed of operation of the circuit during the evaluate phase. As another example, U.S. Pat. No. 5,821,778, entitled “Using cascode transistors having low threshold voltages,” issued Oct. 13, 1998, and is also hereby incorporated herein by reference. In U.S. Pat. No. 5,821,778, there is described a dynamic logic system whereby each discharge path in the system includes at least two low threshold voltage transistors to increase the speed of operation of the circuit during its evaluate phase, but where each of the two low threshold voltage transistors are known to be off during the precharge phase of operation and thereby to improve the leakage characteristics of those transistors and the circuit during that phase.
In addition to the preceding patents, the present inventor now further addresses various of the above-described considerations and drawbacks in the following embodiments, and thereby further improves on the state of the art.
BRIEF SUMMARY OF THE INVENTION
In one embodiment, there is a dynamic logic circuit coupled between an upper supply voltage and a lower supply voltage and operable in an active mode and in a power down mode, where the active mode comprises a precharge phase and an evaluate phase. The dynamic logic circuit comprises a precharge node coupled to be precharged to a precharge voltage during the precharge phase and operable to be discharged during the evaluate phase. The dynamic logic circuit further comprises a conditional series discharge path connected to the precharge node and comprising a plurality of transistors operable to conditionally couple the precharge node to a voltage different than the precharge voltage. Further, the dynamic logic circuit comprises an output inverter having an input connected to the precharge node and comprising a plurality of transistors for providing an output signal representative of a voltage at the precharge node during the evaluate phase. Still further, the dynamic logic circuit comprises a precharge transistor to be enabled during the power down mode and having a source/drain conductive path for coupling the precharge voltage to the precharge node during the precharge phase. Given the above, during the power down mode, at least one transistor in a first set of selected ones of the precharge transistor, the transistors of the conditional series path, and the transistors of the output inverter has a source/drain node connected to the upper supply voltage, and also during the power down mode, at least one transistor in a second set of selected ones of the precharge transistor, the transistors of the conditional series path, and the transistors of the output inverter has a source/drain node connected to the lower supply voltage, and lastly during the power down mode, at least one transistor in a third set of selected ones of the precharge transistor, the transistors of the conditional series path, and the transistors of the output inverter has a source/drain node selectively disabled from either of the upper supply voltage and the lower supply voltage. Other circuits, systems, and methods are also disclosed and claimed.


REFERENCES:
patent: 5712826 (1998-01-01), Wong et al.
patent: 5821778 (1998-10-01), Bosshart

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