Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-11-16
2001-05-08
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S300000, C257S309000, C257S390000, C257S532000
Reexamination Certificate
active
06229172
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a structure of a DRAM (Dynamic Random Access Memory) and a method of manufacturing the same.
2. Description of the Background Art
In recent years, there has been a rapidly increasing demand for semiconductor devices owing to wide spread of information equipment such as computers. In terms of functionality, devices having a larger storage capacity and a high-speed operability have been demanded. To this end, technical development has been proceeded for attaining higher degree of integration and higher response or reliability of semiconductor devices.
Among the semiconductor devices, a DRAM is well-known as a kind permitting random input/output of storage information. The DRAM is formed of a memory cell array region, which is a storage region for storing a large amount of storage information, and a peripheral region necessary for external input and output.
In the DRAM having such a structure, the memory cell array region occupies a large area, and has a plurality of memory cells arranged in a matrix each for storing unit storage information. A memory cell generally consists of one MOS (Metal Oxide Semiconductor) transistor and one capacitor connected thereto, and thus is well-known as a one-transistor and one-capacitor type memory cell.
In the following, a configuration of a conventional DRAM will be described by way of example.
FIG. 20
is a top plan view showing a configuration of a conventional DRAM. Referring to
FIG. 20
, the conventional DRAM includes a memory cell block
504
with a memory capacitor region
504
b
and a dummy capacitor region
504
a
, as a memory cell array region, and a word line contact portion
505
and a sense amplifier contact portion
506
together as a peripheral region. Word line contact portion
505
and sense amplifier contact portion
506
surround memory cell block
504
.
In memory cell block
504
, a plurality of capacitors
521
a
,
522
a
,
523
a
,
531
a
,
532
b
,
533
b
,
541
a
,
542
b
and
543
b
are formed in a matrix, and the capacitors have respective lower electrodes
621
a
,
622
a
,
623
a
,
631
a
,
632
b
,
633
b
,
641
a
,
642
b
and
643
b
therein.
Capacitors
532
b
,
533
b
,
542
b
and
543
b
in memory capacitor region
504
b
are involved in storing information. On the other hand, capacitors
521
a
,
522
a
,
523
a
,
531
a
and
541
a
in dummy capacitor region
504
a
which is adjacent to word line contact portion
505
and sense amplifier contact portion
506
forming a peripheral region take no part in storing information. The capacitors in the peripheral portion of memory cell block
504
are not used for storing information, because those capacitors may not be formed as designed due to discontinuity of minute repetitive patterns or to the presence of steps.
In word line contact portion
505
, an interconnection
572
to be connected to a word line is formed extending in one direction, which is electrically connected to the semiconductor substrate through a contact hole
554
.
FIG. 21
is a cross sectional view taken along the line XXI—XXI in FIG.
20
. With reference to
FIG. 21
, a plurality of MOS transistors (not shown) are formed on the surface
511
a
of a silicon substrate
511
. Formed to cover the MOS transistors is an interlayer insulating film
512
, which is provided with contact holes
513
and
514
.
On the surface
512
a
of interlayer insulating film
512
, lower electrodes
632
b
and
621
a
of the capacitors are formed to fill in respective contact holes
513
and
514
. A dielectric film
551
is formed to cover lower electrodes
621
a
and
632
b
, and to cover dielectric film
551
, an upper electrode
552
of the capacitors is formed. Another interlayer insulating film
553
is formed to cover upper electrode
552
.
Here, lower electrode
621
a
has a relatively high side surface
521
b
, and therefore a step
553
a
is inevitably created in interlayer insulating film
553
in the vicinity of the side surface
521
b
. A contact hole
554
is provided through interlayer insulating films
553
and
512
, and an interconnection
572
is provided on interlayer insulating film
553
to fill in contact hole
554
.
A method of manufacturing the semiconductor device (DRAM) shown in
FIGS. 20 and 21
will now be described.
FIG. 22
is a top plan view showing a manufacturing process of a conventional semiconductor device (DRAM) as shown in
FIGS. 20 and 21
.
FIG. 23
is a cross sectional view taken along the line XXIII—XXIII in FIG.
22
.
Referring to
FIGS. 22 and 23
, a plurality of MOS transistors (not shown) are first formed on silicon substrate
511
. Formed to cover these MOS transistors is an interlayer insulating film
512
, and on which film a resist pattern is formed. Interlayer insulating film
512
is then etched according to this resist pattern to form contact holes
513
and
514
.
Doped polycrystalline silicon (polysilicon) is deposited to fill in contact holes
513
and
514
and to cover interlayer insulating film
512
. This doped polysilicon is etched according to a resist pattern formed thereon, and thus lower electrodes
621
a
,
622
a
,
623
a
,
631
a
,
632
b
,
633
b
,
641
a
,
642
b
and
643
b
are formed. Note that lower electrode
621
a
of the capacitor in this case has a side surface
521
b
of which height (h
0
in
FIG. 23
) is about 700 nm.
A dielectric film is formed to cover these lower electrodes, which is made of a silicon nitride oxide film with a film thickness of about 7 nm. On this dielectric film, a conductive film is formed, which is made of doped polysilicon about 150 nm thick. A resist pattern is formed on the conductive film, and the conductive film as well as the dielectric film are etched according to this resist pattern to form upper electrodes
552
of the capacitors and dielectric film
551
.
An interlayer insulating film
553
is formed to cover upper electrode
552
. At this time, a step
553
a
results in interlayer insulating film
553
in the vicinity of the side surface
521
b
of lower electrode
621
a
. A resist pattern
574
having a hole pattern
574
a
is then formed to cover interlayer insulating film
553
. Here, memory cell block
504
becomes higher in level than word line contact portion
505
and sense amplifier contact portion
506
. Accordingly, the resist for making the resist pattern
574
flows from memory cell block
504
down to word line contact portion
505
and sense amplifier contact portion
506
.
Specifically, as shown in
FIG. 22
, the resist provided on capacitors
521
a
,
522
a
,
523
a
,
531
a
and
541
a
located at the portion adjacent to word line contact portion
505
and sense amplifier contact portion
506
forming the peripheral region flows in the direction shown by arrows
521
c
,
521
d
,
521
e
,
522
c
,
523
c
,
531
c
and
541
c.
In particular, the resist on capacitor
521
a
located at a corner of the matrix will flow mainly in three directions as shown by arrows
521
c
,
521
d
and
521
e
, and therefore the thickness of the resist in this portion (t
1
in
FIG. 23
) will become especially thin, which is about 400 nm.
With reference to
FIGS. 20 and 21
, interlayer insulating films
553
and
512
are etched according to resist pattern
574
to form a contact hole
554
. Doped polysilicon is deposited to fill in contact hole
554
as well as to cover the surface of interlayer insulating film
553
. The doped polysilicon is then etched according to a resist pattern formed thereon, and an interconnection
572
is formed. The DRAM shown in
FIGS. 20 and 21
is thus completed.
FIG. 24
is a cross sectional view illustrating a problem which will arise during the manufacturing process as described above. Referring to
FIG. 24
, when etching interlayer insulating films
553
and
512
according to resist pattern
574
, the resist pattern
574
itself will also be etched away. In this case, on a portion where the thickness of t
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Wojciechowicz Edward
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